kernel/linux.git/drivers/irqchip, branch v6.6

Merge tag 'irq-urgent-2023-10-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2023-10-28T18:12:34+00:00

Pull irq fix from Ingo Molnar: "Restore unintentionally lost quirk settings in the GIC irqchip driver, which broke certain devices" * tag 'irq-urgent-2023-10-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/gic-v3-its: Don't override quirk settings with default values

irqchip/gic-v3-its: Don't override quirk settings with default values

2023-10-25T19:44:49+00:00

When splitting the allocation of the ITS node from its configuration, some of the default settings were kept in the latter instead of being moved to the former. This has the side effect of negating some of the quirk detections that have happened in between, amongst which the dreaded Synquacer hack (that also affect Dominic's TI platform). Move the initialisation of these fields early, so that they can again be overriden by the Synquacer quirk. Fixes: 9585a495ac93 ("irqchip/gic-v3-its: Split allocation from initialisation of its_node") Reported by: Dominic Rath Signed-off-by: Marc Zyngier Signed-off-by: Thomas Gleixner Tested-by: Dominic Rath Link: https://lore.kernel.org/r/20231024084831.GA3788@JADEVM-DRA Link: https://lore.kernel.org/r/20231024143431.2144579-1-maz@kernel.org

Merge tag 'irq-urgent-2023-10-10-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2023-10-10T18:14:07+00:00

Pull irq fixes from Thomas Gleixner: "A set of updates for interrupt chip drivers: - Fix the fail of the Qualcomm PDC driver on v3.2 hardware which is caused by a control bit being moved to a different location - Update the SM8150 device tree PDC resource so the version register can be read - Make the Renesas RZG2L driver correct for interrupts which are outside of the LSB in the TSSR register by using the proper macro for calculating the mask - Document the Renesas RZ2GL device tree binding correctly and update them for a few devices which faul to boot otherwise - Use the proper accessor in the RZ2GL driver instead of blindly dereferencing an unchecked pointer - Make GICv3 handle the dma-non-coherent attribute correctly - Ensure that all interrupt controller nodes on RISCV are marked as initialized correctly Maintainer changes: - Add a new entry for GIC interrupt controllers and assign Marc Zyngier as the maintainer - Remove Marc Zyngier from the core and driver maintainer entries as he is burried in work and short of time to handle that. Thanks to Marc for all the great work he has done in the past couple of years! Also note that commit 5873d380f4c0 ("irqchip/qcom-pdc: Add support for v3.2 HW") has a incorrect SOB chain. The real author is Neil. His patch was posted by Dmitry once and Neil picked it up from the list and reposted it with the bogus SOB chain. Not a big deal, but worth to mention. I wanted to fix that up, but then got distracted and Marc piled more changes on top. So I decided to leave it as is instead of rebasing world" * tag 'irq-urgent-2023-10-10-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: MAINTAINERS: Remove myself from the general IRQ subsystem maintenance MAINTAINERS: Add myself as the ARM GIC maintainer irqchip/renesas-rzg2l: Convert to irq_data_get_irq_chip_data() irqchip/stm32-exti: add missing DT IRQ flag translation irqchip/riscv-intc: Mark all INTC nodes as initialized irqchip/gic-v3: Enable non-coherent redistributors/ITSes DT probing irqchip/gic-v3-its: Split allocation from initialisation of its_node dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property dt-bindings: interrupt-controller: renesas,irqc: Add r8a779f0 support dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC irqchip: renesas-rzg2l: Fix logic to clear TINT interrupt source dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update description for '#interrupt-cells' property arm64: dts: qcom: sm8150: extend the size of the PDC resource irqchip/qcom-pdc: Add support for v3.2 HW

irqchip/renesas-rzg2l: Convert to irq_data_get_irq_chip_data()

2023-10-07T11:47:13+00:00

Use the existing irq_data_get_irq_chip_data() helper instead of open-coding the same operation. Signed-off-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/8e47cc6400e5a82c854c855948d2665a3a3197e3.1695819391.git.geert+renesas@glider.be

irqchip/stm32-exti: add missing DT IRQ flag translation

2023-10-07T11:47:12+00:00

The STM32F4/7 EXTI driver was missing the xlate callback, so IRQ trigger flags specified in the device tree were being ignored. This was preventing the RTC alarm interrupt from working, because it must be set to trigger on the rising edge to function correctly. Signed-off-by: Ben Wolsieffer Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20231003162003.1649967-1-ben.wolsieffer@hefring.com

irqchip/riscv-intc: Mark all INTC nodes as initialized

2023-10-07T11:47:12+00:00

The RISC-V INTC local interrupts are per-HART (or per-CPU) so we create INTC IRQ domain only for the INTC node belonging to the boot HART. This means only the boot HART INTC node will be marked as initialized and other INTC nodes won't be marked which results downstream interrupt controllers (such as PLIC, IMSIC and APLIC direct-mode) not being probed due to missing device suppliers. To address this issue, we mark all INTC node for which we don't create IRQ domain as initialized. Reported-by: Dmitry Dunaev Signed-off-by: Anup Patel Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230926102801.1591126-1-dunaev@tecon.ru Link: https://lore.kernel.org/r/20231003044403.1974628-4-apatel@ventanamicro.com

irqchip/gic-v3: Enable non-coherent redistributors/ITSes DT probing

2023-10-07T11:47:12+00:00

The GIC architecture specification defines a set of registers for redistributors and ITSes that control the sharebility and cacheability attributes of redistributors/ITSes initiator ports on the interconnect (GICR_[V]PROPBASER, GICR_[V]PENDBASER, GITS_BASER). Architecturally the GIC provides a means to drive shareability and cacheability attributes signals and related IWB/OWB/ISH barriers but it is not mandatory for designs to wire up the corresponding interconnect signals that control the cacheability/shareability of transactions. Redistributors and ITSes interconnect ports can be connected to non-coherent interconnects that are not able to manage the shareability/cacheability attributes; this implicitly makes the redistributors and ITSes non-coherent observers. So far, the GIC driver on probe executes a write to "probe" for the redistributors and ITSes registers shareability bitfields by writing a value (ie InnerShareable - the shareability domain the CPUs are in) and check it back to detect whether the value sticks or not; this hinges on a GIC programming model behaviour that predates the current specifications, that just define shareability bits as writeable but do not guarantee that writing certain shareability values enable the expected behaviour for the redistributors/ITSes memory interconnect ports. To enable non-coherent GIC designs, introduce the "dma-noncoherent" device tree property to allow firmware to describe redistributors and ITSes as non-coherent observers on the memory interconnect and use the property to force the shareability attributes to be programmed into the redistributors and ITSes registers through the GIC quirks mechanism. Signed-off-by: Lorenzo Pieralisi Cc: Robin Murphy Cc: Mark Rutland Cc: Marc Zyngier Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20231006125929.48591-3-lpieralisi@kernel.org

irqchip/gic-v3-its: Split allocation from initialisation of its_node

2023-10-07T11:47:12+00:00

In order to pave the way for more fancy quirk handling without making more of a mess of this terrible driver, split the allocation of the ITS descriptor (its_node) from the actual probing. This will allow firmware-specific hooks to be added between these two points. Signed-off-by: Marc Zyngier Signed-off-by: Lorenzo Pieralisi Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20231006125929.48591-4-lpieralisi@kernel.org

irqchip: renesas-rzg2l: Fix logic to clear TINT interrupt source

2023-09-24T09:18:19+00:00

The logic to clear the TINT interrupt source in rzg2l_irqc_irq_disable() is wrong as the mask is correct only for LSB on the TSSR register. This issue is found when testing with two TINT interrupt sources. So fix the logic for all TINTs by using the macro TSSEL_SHIFT() to multiply tssr_offset with 8. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Biju Das Tested-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Reviewed-by: Claudiu Beznea Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230918122411.237635-2-biju.das.jz@bp.renesas.com

irqchip: irq-xtensa-mx: include header for missing prototype

2023-09-20T12:03:20+00:00

Add to provide the function prototype to prevent a build warning: drivers/irqchip/irq-xtensa-mx.c:166:12: warning: no previous prototype for 'xtensa_mx_init_legacy' [-Wmissing-prototypes] 166 | int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent) Signed-off-by: Randy Dunlap Acked-by: Marc Zyngier Cc: Chris Zankel Cc: Max Filippov Cc: Thomas Gleixner Cc: Marc Zyngier Message-Id: <20230920052139.10570-10-rdunlap@infradead.org> Signed-off-by: Max Filippov