Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.3.y 2019-07-03T08:33:01+00:00 2019-07-03T08:33:01+00:00 Sameer Pujar spujar@nvidia.com 2019-06-20T15:57:48+00:00 urn:sha1:3dae67ce600caaa92c9af6e0cb6cad2db2632a0a gic-pm driver does not use pm-clk interface now and hence the dependency is removed from Kconfig. Signed-off-by: Sameer Pujar <spujar@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2019-07-03T08:19:11+00:00 Talel Shenhar talel@amazon.com 2019-06-10T08:34:43+00:00 urn:sha1:1eb77c3bcdb70f2501f419b3da45b19acaf01072 The Amazon's Annapurna Labs Fabric Interrupt Controller has 32 inputs. A FIC (Fabric Interrupt Controller) may be cascaded into another FIC or directly to the main CPU Interrupt Controller (e.g. GIC). Signed-off-by: Talel Shenhar <talel@amazon.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2019-06-17T09:10:02+00:00 Jiangfeng Xiao xiaojiangfeng@huawei.com 2019-06-14T12:57:09+00:00 urn:sha1:702655234dd1d07e76f9bff9575e438c969fc32c CONFIG_ARM_GIC_MAX_NR is enabled by default. It is redundant in x86 and IA-64 where is without GIC. Signed-off-by: Jiangfeng Xiao <xiaojiangfeng@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2019-06-11T11:18:06+00:00 Geert Uytterhoeven geert+renesas@glider.be 2019-06-07T09:50:36+00:00 urn:sha1:02d7e0417f6e3cde7678b13497f51f314e38b5dc Enable compile-testing for all Renesas interrupt controller drivers, except for RENESAS_H8300H_INTC. The latter relies on a function (ctrl_bclr()) that is not available on other architectures. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2019-05-29T09:42:25+00:00 Geert Uytterhoeven geert+renesas@glider.be 2019-05-27T12:17:11+00:00 urn:sha1:a644ccb819bcf3e4038064fb601b2a07ccd0c315 Add a driver for the Renesas RZ/A1 Interrupt Controller. This supports using up to 8 external interrupts on RZ/A1, with configurable sense select. NMI edge select is not yet supported. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2019-05-21T08:50:46+00:00 Thomas Gleixner tglx@linutronix.de 2019-05-19T12:07:45+00:00 urn:sha1:ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1 Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2019-05-19T17:58:45+00:00 Linus Torvalds torvalds@linux-foundation.org 2019-05-19T17:58:45+00:00 urn:sha1:d9351ea14ddca708d3cb384f828af4bf82fcc772 Pull IRQ chip updates from Ingo Molnar: "A late irqchips update: - New TI INTR/INTA set of drivers - Rewrite of the stm32mp1-exti driver as a platform driver - Update the IOMMU MSI mapping API to be RT friendly - A number of cleanups and other low impact fixes" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits) iommu/dma-iommu: Remove iommu_dma_map_msi_msg() irqchip/gic-v3-mbi: Don't map the MSI page in mbi_compose_m{b, s}i_msg() irqchip/ls-scfg-msi: Don't map the MSI page in ls_scfg_msi_compose_msg() irqchip/gic-v3-its: Don't map the MSI page in its_irq_compose_msi_msg() irqchip/gicv2m: Don't map the MSI page in gicv2m_compose_msi_msg() iommu/dma-iommu: Split iommu_dma_map_msi_msg() in two parts genirq/msi: Add a new field in msi_desc to store an IOMMU cookie arm64: arch_k3: Enable interrupt controller drivers irqchip/ti-sci-inta: Add msi domain support soc: ti: Add MSI domain bus support for Interrupt Aggregator irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings irqchip/ti-sci-intr: Add support for Interrupt Router driver dt-bindings: irqchip: Introduce TISCI Interrupt router bindings gpio: thunderx: Use the default parent apis for {request,release}_resources genirq: Introduce irq_chip_{request,release}_resource_parent() apis firmware: ti_sci: Add helper apis to manage resources firmware: ti_sci: Add RM mapping table for am654 firmware: ti_sci: Add support for IRQ management firmware: ti_sci: Add support for RM core ops ... 2019-05-01T09:49:17+00:00 Lokesh Vutla lokeshvutla@ti.com 2019-04-30T10:12:29+00:00 urn:sha1:f011df6179bdffac63987f009d25dd79b6e2df23 Add a msi domain that is child to the INTA domain. Clients uses the INTA MSI bus layer to allocate irqs in this MSI domain. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2019-05-01T09:49:13+00:00 Lokesh Vutla lokeshvutla@ti.com 2019-04-30T10:12:27+00:00 urn:sha1:9f1463b86c13277d0bd88d5ee359577ef40f4da7 Texas Instruments' K3 generation SoCs has an IP Interrupt Aggregator which is an interrupt controller that does the following: - Converts events to interrupts that can be understood by an interrupt router. - Allows for multiplexing of events to interrupts. Configuration of the interrupt aggregator registers can only be done by a system co-processor and the driver needs to send a message to this co processor over TISCI protocol. Add the required infrastructure to allow the allocation and routing of these events. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 2019-05-01T09:48:56+00:00 Lokesh Vutla lokeshvutla@ti.com 2019-04-30T10:12:25+00:00 urn:sha1:cd844b0715ceda3287d1fa8e5d8e1b25a85c9b0f Texas Instruments' K3 generation SoCs has an IP Interrupt Router that does allows for redirection of input interrupts to host interrupt controller. Interrupt Router inputs are either from a peripheral or from an Interrupt Aggregator which is another interrupt controller. Configuration of the interrupt router registers can only be done by a system co-processor and the driver needs to send a message to this co processor over TISCI protocol. Add support for Interrupt Router driver over TISCI protocol. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>