kernel/linux.git/drivers/gpu, branch v6.4.4

drm/amdgpu: check RAS irq existence for VCN/JPEG

2023-07-19T14:37:02+00:00

commit 4ff96bcc0d40b66bf3ddd6010830e9a4f9b85d53 upstream No RAS irq is allowed. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.1.x Signed-off-by: Greg Kroah-Hartman

drm/amd/pm: add abnormal fan detection for smu 13.0.0

2023-07-19T14:37:01+00:00

commit 2da0036ea99bccb27f7fe3cf2aa2900860e9be46 upstream add abnormal fan detection for smu 13.0.0 Signed-off-by: Kenneth Feng Reviewed-by: Evan Quan Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.1.x Signed-off-by: Greg Kroah-Hartman

drm/amdgpu/sdma4: set align mask to 255

2023-07-19T14:37:01+00:00

commit e5df16d9428f5c6d2d0b1eff244d6c330ba9ef3a upstream The wptr needs to be incremented at at least 64 dword intervals, use 256 to align with windows. This should fix potential hangs with unaligned updates. Reviewed-by: Felix Kuehling Reviewed-by: Aaron Liu Reviewed-by: Christian König Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman

drm/amd/pm: revise the ASPM settings for thunderbolt attached scenario

2023-07-19T14:37:01+00:00

commit fd21987274463a439c074b8f3c93d3b132e4c031 upstream Also, correct the comment for NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT as 0x0000000E stands for 400ms instead of 4ms. Signed-off-by: Evan Quan Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman

drm/amdgpu: Skip mark offset for high priority rings

2023-07-19T14:37:01+00:00

commit ef3c36a6e025e9b16ca3321479ba016841fa17a0 upstream Only low priority rings are using chunks to save the offset. Bypass the mark offset callings from high priority rings. Signed-off-by: Jiadong Zhu Acked-by: Alex Deucher Signed-off-by: Alex Deucher (cherry picked from commit ef3c36a6e025e9b16ca3321479ba016841fa17a0) Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman

drm/amdgpu: make sure that BOs have a backing store

2023-07-19T14:37:01+00:00

commit ca0b954a4315ca2228001c439ae1062561c81989 upstream It's perfectly possible that the BO is about to be destroyed and doesn't have a backing store associated with it. Signed-off-by: Christian König Reviewed-by: Alex Deucher Acked-by: Guchun Chen Tested-by: Mikhail Gavrilov Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.3.x Signed-off-by: Greg Kroah-Hartman

drm/amdgpu: make sure BOs are locked in amdgpu_vm_get_memory

2023-07-19T14:37:01+00:00

commit e2ad8e2df432498b1cee2af04df605723f4d75e6 upstream. We need to grab the lock of the BO or otherwise can run into a crash when we try to inspect the current location. Signed-off-by: Christian König Reviewed-by: Alex Deucher Acked-by: Guchun Chen Tested-by: Mikhail Gavrilov Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.3.x Signed-off-by: Greg Kroah-Hartman

Revert "drm/amd/display: Move DCN314 DOMAIN power control to DMCUB"

2023-07-19T14:36:50+00:00

[ Upstream commit bf0097c5c9aec528da75e2b5fcede472165322bb ] This reverts commit e383b12709e32d6494c948422070c2464b637e44. Controling hubp power gating using the DMCUB isn't stable so we are reverting this change to move control back into the driver. Cc: stable@vger.kernel.org # 6.3+ Reviewed-by: Nicholas Kazlauskas Acked-by: Hamza Mahfooz Signed-off-by: Daniel Miess Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/i915/psr: Fix BDW PSR AUX CH data register offsets

2023-07-19T14:36:47+00:00

[ Upstream commit fdffb7dbc74f48cb1d404d9ab0c9fd769a59caf0 ] The multiplication got replaced by an addition in some cleanup. This means we never write the correct data to some of the BDW PSR data registers and thus we fail to actually wake up the panel from PSR. Fixes: 4ab4fa103217 ("drm/i915/psr: Make PSR registers relative to transcoders") Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-3-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander (cherry picked from commit 460dc4ba1442b3e5e543328d11db2702b98d3d7c) Signed-off-by: Tvrtko Ursulin Signed-off-by: Sasha Levin

drm/amd: Don't try to enable secure display TA multiple times

2023-07-19T14:36:45+00:00

[ Upstream commit 5c6d52ff4b61e5267b25be714eb5a9ba2a338199 ] If the securedisplay TA failed to load the first time, it's unlikely to work again after a suspend/resume cycle or reset cycle and it appears to be causing problems in futher attempts. Fixes: e42dfa66d592 ("drm/amdgpu: Add secure display TA load for Renoir") Reported-by: Filip Hejsek Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2633 Signed-off-by: Mario Limonciello Acked-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin