<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/nova-core/gsp/boot.rs, branch v7.1</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v7.1</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v7.1'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2026-04-06T01:06:39+00:00</updated>
<entry>
<title>gpu: nova-core: fix missing colon in SEC2 boot debug message</title>
<updated>2026-04-06T01:06:39+00:00</updated>
<author>
<name>David Carlier</name>
<email>devnexen@gmail.com</email>
</author>
<published>2026-03-31T10:37:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a7a080bb4236ebe577b6776d940d1717912ff6dd'/>
<id>urn:sha1:a7a080bb4236ebe577b6776d940d1717912ff6dd</id>
<content type='text'>
The SEC2 mailbox debug output formats MBOX1 without a colon separator,
producing "MBOX10xdead" instead of "MBOX1: 0xdead". The GSP debug
message a few lines above uses the correct format.

Fixes: 5949d419c193 ("gpu: nova-core: gsp: Boot GSP")
Signed-off-by: David Carlier &lt;devnexen@gmail.com&gt;
Link: https://patch.msgid.link/20260331103744.605683-1-devnexen@gmail.com
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: convert PFB registers to kernel register macro</title>
<updated>2026-03-26T06:08:27+00:00</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2026-03-25T02:46:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=797385890759d6a011ccd7a028eed6c43142450b'/>
<id>urn:sha1:797385890759d6a011ccd7a028eed6c43142450b</id>
<content type='text'>
Convert all PFB registers to use the kernel's register macro and update
the code accordingly.

NV_PGSP_QUEUE_HEAD was somehow caught in the PFB section, so move it to
its own section and convert it as well.

Reviewed-by: Eliot Courtney &lt;ecourtney@nvidia.com&gt;
Reviewed-by: Gary Guo &lt;gary@garyguo.net&gt;
Acked-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
Link: https://patch.msgid.link/20260325-b4-nova-register-v4-4-bdf172f0f6ca@nvidia.com
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: convert PBUS registers to kernel register macro</title>
<updated>2026-03-26T06:08:27+00:00</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2026-03-25T02:46:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4e7588dcb0a7fef0e709f6907fc42bb7d7458038'/>
<id>urn:sha1:4e7588dcb0a7fef0e709f6907fc42bb7d7458038</id>
<content type='text'>
Convert all PBUS registers to use the kernel's register macro and update
the code accordingly.

Reviewed-by: Eliot Courtney &lt;ecourtney@nvidia.com&gt;
Reviewed-by: Gary Guo &lt;gary@garyguo.net&gt;
Acked-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
Link: https://patch.msgid.link/20260325-b4-nova-register-v4-3-bdf172f0f6ca@nvidia.com
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: use Coherent::init to initialize GspFwWprMeta</title>
<updated>2026-03-23T21:36:00+00:00</updated>
<author>
<name>Danilo Krummrich</name>
<email>dakr@kernel.org</email>
</author>
<published>2026-03-20T19:45:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e21ad5e51c889e4b40a2a3d48363cbed9b047a68'/>
<id>urn:sha1:e21ad5e51c889e4b40a2a3d48363cbed9b047a68</id>
<content type='text'>
Convert wpr_meta to use Coherent::init() and simplify the
initialization.  It also avoids a separate initialization of
GspFwWprMeta on the stack.

Reviewed-by: Gary Guo &lt;gary@garyguo.net&gt;
Reviewed-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Link: https://patch.msgid.link/20260320194626.36263-7-dakr@kernel.org
Signed-off-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: gsp: add mutex locking to Cmdq</title>
<updated>2026-03-18T12:53:14+00:00</updated>
<author>
<name>Eliot Courtney</name>
<email>ecourtney@nvidia.com</email>
</author>
<published>2026-03-18T04:07:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a19457958c3018783881c4416f272cd594f13049'/>
<id>urn:sha1:a19457958c3018783881c4416f272cd594f13049</id>
<content type='text'>
Wrap `Cmdq`'s mutable state in a new struct `CmdqInner` and wrap that in
a Mutex. This lets `Cmdq` methods take &amp;self instead of &amp;mut self, which
lets required commands be sent e.g. while unloading the driver.

The mutex is held over both send and receive in `send_command` to make
sure that it doesn't get the reply of some other command that could have
been sent just beforehand.

Reviewed-by: Zhi Wang &lt;zhiw@nvidia.com&gt;
Tested-by: Zhi Wang &lt;zhiw@nvidia.com&gt;
Signed-off-by: Eliot Courtney &lt;ecourtney@nvidia.com&gt;
Link: https://patch.msgid.link/20260318-cmdq-locking-v5-5-18b37e3f9069@nvidia.com
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: gsp: add reply/no-reply info to `CommandToGsp`</title>
<updated>2026-03-18T12:53:14+00:00</updated>
<author>
<name>Eliot Courtney</name>
<email>ecourtney@nvidia.com</email>
</author>
<published>2026-03-18T04:07:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c3bd240f97491122e3c9e9922def7e59eecd6145'/>
<id>urn:sha1:c3bd240f97491122e3c9e9922def7e59eecd6145</id>
<content type='text'>
Add type infrastructure to know what reply is expected from each
`CommandToGsp`. Uses a marker type `NoReply` which does not implement
`MessageFromGsp` to mark commands which don't expect a response.

Update `send_command` to wait for a reply and add `send_command_no_wait`
which sends a command that has no reply, without blocking.

This prepares for adding locking to the queue.

Tested-by: Zhi Wang &lt;zhiw@nvidia.com&gt;
Reviewed-by: Gary Guo &lt;gary@garyguo.net&gt;
Signed-off-by: Eliot Courtney &lt;ecourtney@nvidia.com&gt;
Link: https://patch.msgid.link/20260318-cmdq-locking-v5-3-18b37e3f9069@nvidia.com
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v7.0-rc4' into drm-rust-next</title>
<updated>2026-03-15T21:58:48+00:00</updated>
<author>
<name>Danilo Krummrich</name>
<email>dakr@kernel.org</email>
</author>
<published>2026-03-15T20:55:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=76bce7ac51673640a4a46236ea723cf5543268d7'/>
<id>urn:sha1:76bce7ac51673640a4a46236ea723cf5543268d7</id>
<content type='text'>
We need the latest fixes from drm-rust-fixes in drm-rust-next as well to
build on top of.

Signed-off-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: add FbRange.len() and use it in boot.rs</title>
<updated>2026-03-10T11:13:46+00:00</updated>
<author>
<name>John Hubbard</name>
<email>jhubbard@nvidia.com</email>
</author>
<published>2026-03-10T02:10:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a247f8a107b5ddbf21084599ad8d8190d1357de8'/>
<id>urn:sha1:a247f8a107b5ddbf21084599ad8d8190d1357de8</id>
<content type='text'>
A tiny simplification: now that FbLayout uses its own specific FbRange
type, add an FbRange.len() method, and use that to (very slightly)
simplify the calculation of Frts::frts_size initialization.

Suggested-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Reviewed-by: Gary Guo &lt;gary@garyguo.net&gt;
Signed-off-by: John Hubbard &lt;jhubbard@nvidia.com&gt;
Link: https://patch.msgid.link/20260310021125.117855-3-jhubbard@nvidia.com
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing</title>
<updated>2026-03-09T01:39:13+00:00</updated>
<author>
<name>Timur Tabi</name>
<email>ttabi@nvidia.com</email>
</author>
<published>2026-03-06T04:52:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=50b3e0c7c82f32e6ac3ead30f0e0ba96d36a4ff6'/>
<id>urn:sha1:50b3e0c7c82f32e6ac3ead30f0e0ba96d36a4ff6</id>
<content type='text'>
On Turing and GA100, a new firmware image called the Generic Bootloader
(gen_bootloader) must be used to load FWSEC into Falcon memory.  The
driver loads the generic bootloader into Falcon IMEM, passes a
descriptor that points to FWSEC using DMEM, and then boots the generic
bootloader.  The bootloader will then load FWSEC into IMEM and boot it.

Signed-off-by: Timur Tabi &lt;ttabi@nvidia.com&gt;
Co-developed-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
Acked-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
Link: https://patch.msgid.link/20260306-turing_prep-v11-12-8f0042c5d026@nvidia.com
</content>
</entry>
<entry>
<title>gpu: nova-core: create falcon firmware DMA objects lazily</title>
<updated>2026-03-09T01:35:37+00:00</updated>
<author>
<name>Alexandre Courbot</name>
<email>acourbot@nvidia.com</email>
</author>
<published>2026-03-06T04:52:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=bc9de9e1af2f05461460e1b215a6d209ee62d65a'/>
<id>urn:sha1:bc9de9e1af2f05461460e1b215a6d209ee62d65a</id>
<content type='text'>
When DMA was the only loading option for falcon firmwares, we decided to
store them in DMA objects as soon as they were loaded from disk and
patch them in-place to avoid having to do an extra copy.

This decision complicates the PIO loading patch considerably, and
actually does not even stand on its own when put into perspective with
the fact that it requires 8 unsafe statements in the code that wouldn't
exist if we stored the firmware into a `KVVec` and copied it into a DMA
object at the last minute.

The cost of the copy is, as can be expected, imperceptible at runtime.
Thus, switch to a lazy DMA object creation model and simplify our code
a bit. This will also have the nice side-effect of being more fit for
PIO loading.

Reviewed-by: Eliot Courtney &lt;ecourtney@nvidia.com&gt;
Acked-by: Danilo Krummrich &lt;dakr@kernel.org&gt;
Link: https://patch.msgid.link/20260306-turing_prep-v11-1-8f0042c5d026@nvidia.com
[acourbot@nvidia.com: add TODO item to switch back to a coherent
allocation when it becomes convenient to do so.]
Signed-off-by: Alexandre Courbot &lt;acourbot@nvidia.com&gt;
</content>
</entry>
</feed>
