kernel/linux.git/drivers/gpu/nova-core/fb.rs, branch v7.2-rc1

gpu: nova-core: move lifetime to `Bar0`

2026-06-03T20:10:51+00:00

Currently Nova code uses `&'a Bar0` a lot. This is `&'a Mmio`, where `Mmio` represents an owned MMIO region; this type only exists as a target for `Deref` so `Bar` and `IoMem` can share code and should be avoided to be named directly. The upcoming I/O projection series would make `Io` trait much simpler to implement, and thus the owned MMIO type would be removed in favour of direct `Io` implementation on `Bar` and `IoMem`. Add lifetime parameter to `Bar0<'a>` and change it to be alias of `&'a pci::Bar<'a, ..>`. This also prepares Nova core so that when I/O projection series land, this could be changed to using a MMIO view type directly which avoids double indirection. Signed-off-by: Gary Guo Acked-by: Alexandre Courbot Reviewed-by: Eliot Courtney Link: https://patch.msgid.link/20260602170416.2268531-1-gary@kernel.org [ Rebase onto latest drm-rust-next (Blackwell enablement). - Danilo ] Signed-off-by: Danilo Krummrich

gpu: nova-core: Hopper/Blackwell: larger non-WPR heap

2026-06-02T13:33:15+00:00

Hopper and Blackwell need a larger non-WPR heap than the 1 MiB that earlier architectures use. Hopper and Blackwell GB10x need 2 MiB, while Blackwell GB20x needs 2 MiB + 128 KiB. These sizes diverge by family, so give Hopper and each Blackwell family its own framebuffer HAL and select the non-WPR heap size per chipset family. Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney Link: https://patch.msgid.link/20260602032111.224790-5-jhubbard@nvidia.com Signed-off-by: Alexandre Courbot

gpu: nova-core: Blackwell: compute PMU-reserved framebuffer size

2026-06-02T13:33:15+00:00

GSP boot needs to know how much framebuffer memory is reserved for the PMU. Compute it per architecture: Blackwell dGPUs reserve a non-zero amount, earlier architectures leave it at zero, matching Open RM behavior. Signed-off-by: John Hubbard Reviewed-by: Eliot Courtney Link: https://patch.msgid.link/20260602032111.224790-4-jhubbard@nvidia.com Co-developed-by: Alexandre Courbot Signed-off-by: Alexandre Courbot

gpu: nova-core: replace ARef with &'bound Device in SysmemFlush

2026-05-29T00:08:41+00:00

Now that SysmemFlush is lifetime-parameterized, the ARef is unnecessary -- a plain &'bound Device reference suffices. Reviewed-by: Eliot Courtney Reviewed-by: Alexandre Courbot Tested-by: Alexandre Courbot Link: https://patch.msgid.link/20260525225838.276108-4-dakr@kernel.org Signed-off-by: Danilo Krummrich

gpu: nova-core: unregister sysmem flush page from Drop

2026-05-29T00:08:03+00:00

Now that SysmemFlush can borrow the Bar via HRT lifetime, store a &'bound Bar0 reference and implement Drop to automatically unregister the sysmem flush page. This removes the need for manual unregister() calls and the Gpu::unbind() method. Reported-by: Eliot Courtney Closes: https://lore.kernel.org/all/20260409-fix-systemflush-v1-1-a1d6c968f17c@nvidia.com/ Fixes: 6554ad65b589 ("gpu: nova-core: register sysmem flush page") Reviewed-by: Eliot Courtney Reviewed-by: Alexandre Courbot Tested-by: Alexandre Courbot Link: https://patch.msgid.link/20260525225838.276108-3-dakr@kernel.org Signed-off-by: Danilo Krummrich

gpu: nova-core: make WPR heap sizing fallible

2026-04-30T01:02:44+00:00

Make management_overhead() fail on multiplication or alignment overflow instead of silently saturating. Propagate that failure through wpr_heap_size() and the framebuffer layout code that consumes it. Signed-off-by: John Hubbard Link: https://patch.msgid.link/20260326013902.588242-27-jhubbard@nvidia.com [acourbot: remove unrelated WPR2 mention from commit log.] Signed-off-by: Alexandre Courbot

gpu: nova-core: add FbHal::frts_size() for GA100 support

2026-04-28T23:27:53+00:00

Introduce FbHal method frts_size() to return the size of the FRTS window. GA100 is a special case in that although there is an FRTS, its size must arbitrarily be set to 0. Note that we cannot use supports_display() to determine the FRTS size because there are other GPUs (e.g. GA102GL) that have display disabled (and so supports_display() returns False), but the FRTS window size still needs to be 1MB. Signed-off-by: Timur Tabi Reviewed-by: Eliot Courtney Acked-by: Gary Guo Link: https://patch.msgid.link/20260417191359.1307434-5-ttabi@nvidia.com [acourbot: apply requested fix to commit message.] [acourbot: fix minor conflict.] Signed-off-by: Alexandre Courbot

gpu: nova-core: use SizeConstants trait for u64 size constants

2026-04-28T22:57:54+00:00

Replace manual usize-to-u64 conversions of SZ_* constants with the SizeConstants trait's associated constants on u64. With the SizeConstants trait in scope, u64::SZ_1M replaces usize_as_u64(SZ_1M) and similar. This removes several now-unused imports: usize_as_u64, FromSafeCast, and individual SZ_* type-level constants. Reviewed-by: Eliot Courtney Reviewed-by: Joel Fernandes Acked-by: Gary Guo Signed-off-by: John Hubbard Link: https://patch.msgid.link/20260411024118.471294-2-jhubbard@nvidia.com Signed-off-by: Danilo Krummrich

gpu: nova-core: fb: use dma::CoherentHandle

2026-03-28T13:20:08+00:00

Replace the nova-core local `DmaObject` with a `CoherentHandle` that can fulfill the same role. Reviewed-by: Danilo Krummrich Link: https://patch.msgid.link/20260327-b4-nova-dma-removal-v2-5-616e1d0b5cb3@nvidia.com Signed-off-by: Alexandre Courbot

gpu: nova-core: convert PDISP registers to kernel register macro

2026-03-26T06:08:28+00:00

Convert all PDISP registers to use the kernel's register macro and update the code accordingly. Reviewed-by: Eliot Courtney Reviewed-by: Joel Fernandes Reviewed-by: Gary Guo Acked-by: Danilo Krummrich Link: https://patch.msgid.link/20260325-b4-nova-register-v4-7-bdf172f0f6ca@nvidia.com Signed-off-by: Alexandre Courbot