kernel/linux.git/drivers/gpu/nova-core/falcon, branch v6.19.11

gpu: nova-core: sequencer: Implement core resume operation

2025-11-15T12:54:18+00:00

Implement core resume operation. This is the last step of the sequencer resulting in resume of the GSP and proceeding to INIT_DONE stage of GSP boot. Signed-off-by: Joel Fernandes Reviewed-by: Lyude Paul Signed-off-by: Alexandre Courbot Message-ID: <20251114195552.739371-12-joelagnelf@nvidia.com>

gpu: nova-core: gsp: Add support for checking if GSP reloaded

2025-11-15T11:08:49+00:00

During the sequencer process, we need to check if GSP was successfully reloaded. Add functionality to check for the same. Reviewed-by: Lyude Paul Signed-off-by: Joel Fernandes Signed-off-by: Alexandre Courbot Message-ID: <20251114195552.739371-6-joelagnelf@nvidia.com>

gpu: nova-core: apply the one "use" item per line policy

2025-11-07T14:10:44+00:00

As per [1], we need one "use" item per line, in order to reduce merge conflicts. Furthermore, we need a trailing ", //" in order to tell rustfmt(1) to leave it alone. This does that for the entire nova-core driver. [1] https://docs.kernel.org/rust/coding-guidelines.html#imports Acked-by: Danilo Krummrich Signed-off-by: John Hubbard [acourbot@nvidia.com: remove imports already in prelude as pointed out by Danilo.] [acourbot@nvidia.com: remove a few unneeded trailing `//`.] Signed-off-by: Alexandre Courbot Message-ID: <20251107021006.434109-1-jhubbard@nvidia.com>

gpu: nova-core: replace `as` with `from` conversions where possible

2025-10-30T01:35:34+00:00

The `as` operator is best avoided as it silently drops bits if the destination type is smaller that the source. For data types where this is clearly not the case, use `from` to unambiguously signal that these conversions are lossless. Acked-by: Danilo Krummrich Signed-off-by: Alexandre Courbot Message-ID: <20251029-nova-as-v3-1-6a30c7333ad9@nvidia.com>

gpu: nova-core: replace wait_on with kernel equivalents

2025-10-25T04:14:21+00:00

wait_on was a temporary helper function waiting for a kernel crate equivalent. Now that read_poll_timeout and fsleep are available, use them and remove wait_on. Acked-by: Danilo Krummrich Signed-off-by: Alexandre Courbot Message-ID: <20251020-nova_wait_on-v1-1-2eb87fb38d14@nvidia.com>

gpu: nova-core: Ada: basic GPU identification

2025-10-25T04:12:05+00:00

...which is sufficient to make Ada GPUs work, because they use the pre-existing Ampere GPU code, unmodified. Tested on AD102 (RTX 6000 Ada). Signed-off-by: John Hubbard Signed-off-by: Alexandre Courbot Message-ID: <20251025012017.573078-1-jhubbard@nvidia.com>

gpu: nova-core: require `Send` on `FalconEngine` and `FalconHal`

2025-09-13T14:17:18+00:00

We want to store the GSP and SEC2 falcon instances inside the `Gpu` structure, but doing so require these types to implement `Send` for `pci::Driver` to remain implementable on `NovaCore`, which embeds `Gpu`. All implementors of `FalconEngine` and `FalconHal` satisfy the requirements of `Send`, and these traits also already required `Sync`, so this a minor tweak. Acked-by: Danilo Krummrich Link: https://lore.kernel.org/r/20250913-nova_firmware-v6-1-9007079548b0@nvidia.com Signed-off-by: Alexandre Courbot

gpu: nova-core: register: add support for relative array registers

2025-08-15T03:02:56+00:00

Add support for declaring arrays of registers available from a variable base. This is effectively a combination of the relative and array registers features. nova-core does not make much use of this yet, but it will become helpful to have for GSP boot. Reviewed-by: Lyude Paul Link: https://lore.kernel.org/r/20250718-nova-regs-v2-19-7b6a762aa1cd@nvidia.com Signed-off-by: Alexandre Courbot

gpu: nova-core: falcon: use register arrays for FUSE registers

2025-08-15T03:02:56+00:00

FUSE registers are an array of 16 consecutive registers. Use the newly available register array feature to define them properly and improve the code using them. Reviewed-by: Lyude Paul Link: https://lore.kernel.org/r/20250718-nova-regs-v2-18-7b6a762aa1cd@nvidia.com Signed-off-by: Alexandre Courbot

gpu: nova-core: falcon: add distinct base address for PFALCON2

2025-08-15T03:02:56+00:00

Falcon engines have two distinct register bases: `PFALCON` and `PFALCON2`. So far we assumed that `PFALCON2` was located at `PFALCON + 0x1000` because that is the case of most engines, but there are exceptions (NVDEC uses `0x1c00`). Fix this shortcoming by leveraging the redesigned relative registers definitions to assign a distinct `PFalcon2Base` base address to each falcon engine. Reviewed-by: Lyude Paul Link: https://lore.kernel.org/r/20250718-nova-regs-v2-16-7b6a762aa1cd@nvidia.com Signed-off-by: Alexandre Courbot