kernel/linux.git/drivers/gpu/ipu-v3, branch v4.12.9

gpu: ipu-v3: Fix CSI selection for VDIC

2017-06-06T08:21:34+00:00

The description of the CSI_SEL bit in the i.MX6 reference manual is incorrect. It states "This bit defines which CSI is the input to the IC. This bit is effective only if IC_INPUT is bit cleared". From experiment it was found this is in fact not correct. The CSI_SEL bit selects which CSI is input to _both_ the VDIC _and_ the IC. If the IC_INPUT bit is set so that the IC is receiving from the VDIC, the IC ignores the CSI_SEL bit, but CSI_SEL still selects which CSI the VDIC receives from in that case. Signed-off-by: Marek Vasut Signed-off-by: Steve Longerbeam Signed-off-by: Philipp Zabel

gpu: ipu-v3: pre: only use internal clock gating

2017-06-06T08:21:10+00:00

By setting the SFTRST bit, the PRE will be held in the lowest power state with clocks to the internal blocks gated. When external clock gating is used (from the external clock controller, or by setting the CLKGATE bit) the PRE will sporadically fail to start. Signed-off-by: Lucas Stach Fixes: d2a34232580a ("gpu: ipu-v3: add driver for Prefetch Resolve Engine") Signed-off-by: Philipp Zabel

gpu: ipu-v3: don't depend on DRM being enabled

2017-04-04T08:58:56+00:00

The PRE/PRG drivers, which need the DRM infrastructure, are only used from the output path, so we skip building them into the ipu-v3 driver if CONFIG_DRM is not enabled. Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel

gpu: ipu-v3: only set non-zero AXI ID for IC when PRG is absent

2017-03-16T09:14:49+00:00

Using non-zero AXI IDs for anything other than the display channels collides with the PRG AXI snooping, so only do this if there is no PRG present. Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel

gpu: ipu-v3: hook up PRG unit

2017-03-16T09:14:39+00:00

The i.MX6 QuadPlus IPU needs to PRG unit to gain access to the data bus. Make sure it is present and available to be used. Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel

gpu: ipu-v3: add driver for Prefetch Resolve Gasket

2017-03-16T09:14:02+00:00

This adds support for the i.MX6 QUadPlus PRG unit. It glues together the IPU and the PRE units. Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel --- v4: add missing ipu_soc->prg_priv

gpu: ipu-v3: add driver for Prefetch Resolve Engine

2017-03-15T14:42:35+00:00

This adds support for the i.MX6 QuadPlus PRE units. Currently only linear prefetch into SRAM is supported, other modes of operation like the tiled-to-linear conversion will be added later. Signed-off-by: Lucas Stach Signed-off-by: Philipp Zabel

gpu: ipu-v3: add support for separate alpha channels

2017-03-15T14:42:31+00:00

The IPUv3 can read 8-bit alpha values from a separate IDMAC channel driven by the Alpha Transparency Controller (ATC) for the graphics IDMAC channels. This allows to reduce memory bandwidth via a conditional read mechanism or to support planar YUV formats with alpha transparency. Signed-off-by: Philipp Zabel

drm/imx: add deferred plane disabling

2017-03-15T14:42:29+00:00

The DP (display processor) channel disable code tried to busy wait for the DP sync flow end interrupt status bit when disabling the partial plane without a full modeset. That never worked reliably, and it was disabled completely by the recent "gpu: ipu-v3: remove IRQ dance on DC channel disable" patch, causing ipu_wait_interrupt to always time out after 50 ms, which in turn would trigger a timeout in drm_atomic_helper_wait_for_vblanks. This patch changes ipu_plane_atomic_disable to only queue a DP channel register update at the next frame boundary and set a flag, which can be done without any waiting whatsoever. The imx_drm_atomic_commit_tail then calls a new ipu_plane_disable_deferred function that does the actual IDMAC teardown of the planes that are flagged for deferred disabling, after waiting for the vblank. Signed-off-by: Philipp Zabel Reviewed-by: Lucas Stach

gpu: ipu-v3: add unsynchronised DP channel disabling

2017-03-15T14:28:27+00:00

When disabling the foreground DP channel during a modeset, the DC is already disabled without waiting for end of frame. There is no reason to wait for a frame boundary before updating the DP registers in that case. Add support to apply updates immediately. No functional changes, yet. Signed-off-by: Philipp Zabel Reviewed-by: Lucas Stach