kernel/linux.git/drivers/gpu/host1x/hw, branch v6.6.132Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.1322023-01-27T16:41:49+00:00gpu: host1x: Use tegra_dev_iommu_get_stream_id()2023-01-27T16:41:49+00:00Thierry Redingtreding@nvidia.com2022-11-17T12:36:19+00:00urn:sha1:9026ba722360ce5fb72ff7bbc445c49dc9a736ac
Use the newly implemented tegra_dev_iommu_get_stream_id() helper to
encapsulate and centralize the IOMMU stream ID access.
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: External timeout/cancellation for fences2023-01-26T14:55:38+00:00Mikko Perttunenmperttunen@nvidia.com2023-01-19T13:09:21+00:00urn:sha1:d5179020f5ce44fd449790a9c12ef6c1a90a2ca7
Currently all fences have a 30 second timeout to ensure they are
cleaned up if the fence never completes otherwise. However, this
one size fits all solution doesn't actually fit in every case,
such as syncpoint waiting where we want to be able to have timeouts
longer than 30 seconds. As such, we want to be able to give control
over fence cancellation to the caller (and maybe eventually get rid
of the internal timeout altogether).
Here we add this cancellation mechanism by essentially adding a
function for entering the timeout path by function call, and changing
the syncpoint wait function to use it.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Rewrite syncpoint interrupt handling2023-01-26T14:55:38+00:00Mikko Perttunenmperttunen@nvidia.com2023-01-19T13:09:20+00:00urn:sha1:625d4ffb438cacc9b1ebaa48748cdc7171587cdc
Move from the old, complex intr handling code to a new implementation
based on dma_fences. While there is a fair bit of churn to get there,
the new implementation is much simpler and likely faster as well due
to allowing signaling directly from interrupt context.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Implement job tracking using DMA fences2023-01-26T14:55:38+00:00Mikko Perttunenmperttunen@nvidia.com2023-01-19T13:09:19+00:00urn:sha1:c24973ed795fec5c12d8a822a0de99a4b7bab394
In anticipation of removal of the intr API, implement job tracking
using DMA fences instead. The main two things about this are
making cdma_update schedule the work since fence completion can
now be called from interrupt context, and some complication in
ensuring the callback is not running when we free the fence.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Don't skip assigning syncpoints to channels2023-01-26T14:55:38+00:00Mikko Perttunenmperttunen@nvidia.com2023-01-19T13:39:00+00:00urn:sha1:eb258cc1fd458e584082be987dbc6ec42668c05e
The code to write the syncpoint channel assignment register
incorrectly skips the write if hypervisor registers are not available.
The register, however, is within the guest aperture so remove the
check and assign syncpoints properly even on virtualized systems.
Fixes: c3f52220f276 ("gpu: host1x: Enable Tegra186 syncpoint protection")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Fix mask for syncpoint increment register2023-01-26T14:55:38+00:00Mikko Perttunenmperttunen@nvidia.com2023-01-19T13:38:59+00:00urn:sha1:79aad29c7d2d2cd64790115d3a6ebac28c00a8ec
On Tegra186+, the syncpoint ID has 10 bits of space. To allow
using more than 256 syncpoints, fix the mask.
Fixes: 9abdd497cd0a ("gpu: host1x: Tegra234 device data and headers")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Initialize syncval in channel_submit()2022-07-08T15:35:19+00:00Mikko Perttunenmperttunen@nvidia.com2022-07-08T15:18:01+00:00urn:sha1:5b7239c17ce29b4ffea90a5731d56bd8a3893960
During the refactoring of channel_submit(), assignment of syncval was
moved but it is also used in channel_submit(). Add this assignment back
to channel_submit() as well.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Add MLOCK release code on Tegra2342022-07-08T14:27:53+00:00Mikko Perttunenmperttunen@nvidia.com2022-06-27T14:20:06+00:00urn:sha1:a94b8a77bc914db6556e8019cf23d9dda9ab907e
With the full-featured opcode sequence using MLOCKs, we need to also
unlock those MLOCKs in the event of a timeout. However, it turns out
that on Tegra186/Tegra194, by default, we don't need to do this;
furthermore, on Tegra234 it is much simpler to do; so only implement
this on Tegra234 for the time being.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Rewrite job opcode sequence2022-07-08T14:27:53+00:00Mikko Perttunenmperttunen@nvidia.com2022-06-27T14:20:05+00:00urn:sha1:1411796f200de86d037578752450a9853359670c
For new (Tegra186+) SoCs, use a new ('full-featured') job opcode
sequence that is compatible with virtualization. In particular,
the Host1x hardware in Tegra234 is more strict regarding the sequence,
requiring ACQUIRE_MLOCK-SETCLASS-SETSTREAMID opcodes to occur in
that sequence without gaps (except for SETPAYLOAD), so let's do it
properly in one go now.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Tegra234 device data and headers2022-07-08T14:27:52+00:00Mikko Perttunenmperttunen@nvidia.com2022-06-27T14:20:04+00:00urn:sha1:9abdd497cd0ac08ed55aea30de1e46d73eef9fc5
Add device data and chip headers for Tegra234.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>