kernel/linux.git/drivers/gpu/host1x/hw, branch v6.1.168Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.1682023-03-10T08:33:16+00:00gpu: host1x: Don't skip assigning syncpoints to channels2023-03-10T08:33:16+00:00Mikko Perttunenmperttunen@nvidia.com2023-01-19T13:39:00+00:00urn:sha1:7009b78bb995580d8b3d8000ab84ad6f87e811c3
[ Upstream commit eb258cc1fd458e584082be987dbc6ec42668c05e ]
The code to write the syncpoint channel assignment register
incorrectly skips the write if hypervisor registers are not available.
The register, however, is within the guest aperture so remove the
check and assign syncpoints properly even on virtualized systems.
Fixes: c3f52220f276 ("gpu: host1x: Enable Tegra186 syncpoint protection")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
gpu: host1x: Fix mask for syncpoint increment register2023-03-10T08:33:16+00:00Mikko Perttunenmperttunen@nvidia.com2023-01-19T13:38:59+00:00urn:sha1:0906026ac285eb849a05549040f9faa4a9a037a4
[ Upstream commit 79aad29c7d2d2cd64790115d3a6ebac28c00a8ec ]
On Tegra186+, the syncpoint ID has 10 bits of space. To allow
using more than 256 syncpoints, fix the mask.
Fixes: 9abdd497cd0a ("gpu: host1x: Tegra234 device data and headers")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
gpu: host1x: Initialize syncval in channel_submit()2022-07-08T15:35:19+00:00Mikko Perttunenmperttunen@nvidia.com2022-07-08T15:18:01+00:00urn:sha1:5b7239c17ce29b4ffea90a5731d56bd8a3893960
During the refactoring of channel_submit(), assignment of syncval was
moved but it is also used in channel_submit(). Add this assignment back
to channel_submit() as well.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Add MLOCK release code on Tegra2342022-07-08T14:27:53+00:00Mikko Perttunenmperttunen@nvidia.com2022-06-27T14:20:06+00:00urn:sha1:a94b8a77bc914db6556e8019cf23d9dda9ab907e
With the full-featured opcode sequence using MLOCKs, we need to also
unlock those MLOCKs in the event of a timeout. However, it turns out
that on Tegra186/Tegra194, by default, we don't need to do this;
furthermore, on Tegra234 it is much simpler to do; so only implement
this on Tegra234 for the time being.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Rewrite job opcode sequence2022-07-08T14:27:53+00:00Mikko Perttunenmperttunen@nvidia.com2022-06-27T14:20:05+00:00urn:sha1:1411796f200de86d037578752450a9853359670c
For new (Tegra186+) SoCs, use a new ('full-featured') job opcode
sequence that is compatible with virtualization. In particular,
the Host1x hardware in Tegra234 is more strict regarding the sequence,
requiring ACQUIRE_MLOCK-SETCLASS-SETSTREAMID opcodes to occur in
that sequence without gaps (except for SETPAYLOAD), so let's do it
properly in one go now.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Tegra234 device data and headers2022-07-08T14:27:52+00:00Mikko Perttunenmperttunen@nvidia.com2022-06-27T14:20:04+00:00urn:sha1:9abdd497cd0ac08ed55aea30de1e46d73eef9fc5
Add device data and chip headers for Tegra234.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Program interrupt destinations on Tegra2342022-07-08T14:27:52+00:00Mikko Perttunenmperttunen@nvidia.com2022-06-27T14:20:03+00:00urn:sha1:7afd1194a3cdb7ba5aa8d658b2d0655f61457c86
On Tegra234, each Host1x VM has 8 interrupt lines. Each syncpoint
can be configured with which interrupt line should be used for
threshold interrupt, allowing for load balancing.
For now, to keep backwards compatibility, just set all syncpoints
to the first interrupt.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Deduplicate hardware headers2022-07-08T14:27:52+00:00Mikko Perttunenmperttunen@nvidia.com2022-06-27T14:19:59+00:00urn:sha1:3000c4ac02584e877926f598aff501c36202750c
Host1x class information and opcodes are unchanged or backwards
compatible across SoCs so let's not duplicate them for each one
but have them in a shared header file.
At the same time, add opcode functions for acquire/release_mlock.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Program context stream ID on submission2022-07-08T14:27:52+00:00Mikko Perttunenmperttunen@nvidia.com2022-06-27T14:19:49+00:00urn:sha1:2486254781eab6f6119fabea78f11386c54460d2
Add code to do stream ID switching at the beginning of a job. The
stream ID is switched to the stream ID specified by the context
passed in the job structure.
Before switching the stream ID, an OP_DONE wait is done on the
channel's engine to ensure that there is no residual ongoing
work that might do DMA using the new stream ID.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
gpu: host1x: Add initial runtime PM and OPP support2021-12-16T13:07:07+00:00Dmitry Osipenkodigetx@gmail.com2021-11-30T23:23:15+00:00urn:sha1:6b6776e2ab8ac7086cf31ad339411df7681715b7
Add runtime PM and OPP support to the Host1x driver. For the starter we
will keep host1x always-on because dynamic power management require a major
refactoring of the driver code since lot's of code paths are missing the
RPM handling and we're going to remove some of these paths in the future.
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>