<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/xe/xe_vm.h, branch linux-7.1.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.1.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.1.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2026-03-26T01:05:59+00:00</updated>
<entry>
<title>drm/xe/xe_vm: Implement xe_vm_get_property_ioctl</title>
<updated>2026-03-26T01:05:59+00:00</updated>
<author>
<name>Jonathan Cavitt</name>
<email>jonathan.cavitt@intel.com</email>
</author>
<published>2026-03-24T15:29:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=50c577eab051638fbe8989fae1f826ecc1d2e2c7'/>
<id>urn:sha1:50c577eab051638fbe8989fae1f826ecc1d2e2c7</id>
<content type='text'>
Add support for userspace to request a list of observed faults
from a specified VM.

v2:
- Only allow querying of failed pagefaults (Matt Brost)

v3:
- Remove unnecessary size parameter from helper function, as it
  is a property of the arguments. (jcavitt)
- Remove unnecessary copy_from_user (Jainxun)
- Set address_precision to 1 (Jainxun)
- Report max size instead of dynamic size for memory allocation
  purposes.  Total memory usage is reported separately.

v4:
- Return int from xe_vm_get_property_size (Shuicheng)
- Fix memory leak (Shuicheng)
- Remove unnecessary size variable (jcavitt)

v5:
- Rename ioctl to xe_vm_get_faults_ioctl (jcavitt)
- Update fill_property_pfs to eliminate need for kzalloc (Jianxun)

v6:
- Repair and move fill_faults break condition (Dan Carpenter)
- Free vm after use (jcavitt)
- Combine assertions (jcavitt)
- Expand size check in xe_vm_get_faults_ioctl (jcavitt)
- Remove return mask from fill_faults, as return is already -EFAULT or 0
  (jcavitt)

v7:
- Revert back to using xe_vm_get_property_ioctl
- Apply better copy_to_user logic (jcavitt)

v8:
- Fix and clean up error value handling in ioctl (jcavitt)
- Reapply return mask for fill_faults (jcavitt)

v9:
- Future-proof size logic for zero-size properties (jcavitt)
- Add access and fault types (Jianxun)
- Remove address type (Jianxun)

v10:
- Remove unnecessary switch case logic (Raag)
- Compress size get, size validation, and property fill functions into a
  single helper function (jcavitt)
- Assert valid size (jcavitt)

v11:
- Remove unnecessary else condition
- Correct backwards helper function size logic (jcavitt)

v12:
- Use size_t instead of int (Raag)

v13:
- Remove engine class and instance (Ivan)

v14:
- Map access type, fault type, and fault level to user macros (Matt
  Brost, Ivan)

v15:
- Remove unnecessary size assertion (jcavitt)

v16:
- Nit fixes (Matt Brost)

v17:
- Rebase and refactor (jcavitt)

v18:
- Do not copy_to_user in critical section (Matt Brost)
- Assert args-&gt;size is multiple of sizeof(struct xe_vm_fault) (Matt
  Brost)

v19:
- Remove unnecessary memset (Matt Brost)

v20:
- Report canonicalized address (Jose)
- Mask out prefetch data from access type (Jose, jcavitt)

v21:
- s/uAPI/Link in the commit log links
- Align debug parameters

Link: https://github.com/intel/compute-runtime/pull/878
Signed-off-by: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Suggested-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Reviewed-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Acked-by: Michal Mrozek &lt;michal.mrozek@intel.com&gt;
Cc: Jainxun Zhang &lt;jianxun.zhang@intel.com&gt;
Cc: Shuicheng Lin &lt;shuicheng.lin@intel.com&gt;
Cc: Raag Jadav &lt;raag.jadav@intel.com&gt;
Cc: Ivan Briano &lt;ivan.briano@intel.com&gt;
Cc: Jose Souza &lt;jose.souza@intel.com&gt;
Signed-off-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Link: https://patch.msgid.link/20260324152935.72444-10-jonathan.cavitt@intel.com
</content>
</entry>
<entry>
<title>drm/xe/xe_vm: Add per VM fault info</title>
<updated>2026-03-26T01:05:57+00:00</updated>
<author>
<name>Jonathan Cavitt</name>
<email>jonathan.cavitt@intel.com</email>
</author>
<published>2026-03-24T15:29:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=64c732ee2a00a2d6a2693ed25663fa0544c56ba8'/>
<id>urn:sha1:64c732ee2a00a2d6a2693ed25663fa0544c56ba8</id>
<content type='text'>
Add additional information to each VM so they can report up to the first
50 seen faults.  Only pagefaults are saved this way currently, though in
the future, all faults should be tracked by the VM for future reporting.

Additionally, of the pagefaults reported, only failed pagefaults are
saved this way, as successful pagefaults should recover silently and not
need to be reported to userspace.

v2:
- Free vm after use (Shuicheng)
- Compress pf copy logic (Shuicheng)
- Update fault_unsuccessful before storing (Shuicheng)
- Fix old struct name in comments (Shuicheng)
- Keep first 50 pagefaults instead of last 50 (Jianxun)

v3:
- Avoid unnecessary execution by checking MAX_PFS earlier (jcavitt)
- Fix double-locking error (jcavitt)
- Assert kmemdump is successful (Shuicheng)

v4:
- Rename xe_vm.pfs to xe_vm.faults (jcavitt)
- Store fault data and not pagefault in xe_vm faults list (jcavitt)
- Store address, address type, and address precision per fault (jcavitt)
- Store engine class and instance data per fault (Jianxun)
- Add and fix kernel docs (Michal W)
- Properly handle kzalloc error (Michal W)
- s/MAX_PFS/MAX_FAULTS_SAVED_PER_VM (Michal W)
- Store fault level per fault (Micahl M)

v5:
- Store fault and access type instead of address type (Jianxun)

v6:
- Store pagefaults in non-fault-mode VMs as well (Jianxun)

v7:
- Fix kernel docs and comments (Michal W)

v8:
- Fix double-locking issue (Jianxun)

v9:
- Do not report faults from reserved engines (Jianxun)

v10:
- Remove engine class and instance (Ivan)

v11:
- Perform kzalloc outside of lock (Auld)

v12:
- Fix xe_vm_fault_entry kernel docs (Shuicheng)

v13:
- Rebase and refactor (jcavitt)

v14:
- Correctly ignore fault mode in save_pagefault_to_vm (jcavitt)

v15:
- s/save_pagefault_to_vm/xe_pagefault_save_to_vm (Matt Brost)
- Use guard instead of spin_lock/unlock (Matt Brost)
- GT was added to xe_pagefault struct.  Use xe_gt_hw_engine
  instead of creating a new helper function (Matt Brost)

v16:
- Set address precision programmatically (Matt Brost)

v17:
- Set address precision to fixed value (Matt Brost)

v18:
- s/uAPI/Link in commit log links
- Use kzalloc_obj

Link: https://github.com/intel/compute-runtime/pull/878
Signed-off-by: Jonathan Cavitt &lt;jonathan.cavitt@intel.com&gt;
Suggested-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Reviewed-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Cc: Shuicheng Lin &lt;shuicheng.lin@intel.com&gt;
Cc: Jianxun Zhang &lt;jianxun.zhang@intel.com&gt;
Cc: Michal Wajdeczko &lt;Michal.Wajdeczko@intel.com&gt;
Cc: Michal Mzorek &lt;michal.mzorek@intel.com&gt;
Cc: Ivan Briano &lt;ivan.briano@intel.com&gt;
Cc: Matthew Auld &lt;matthew.auld@intel.com&gt;
Cc: Matthew Brost &lt;matthew.brost@intel.com&gt;
Signed-off-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Link: https://patch.msgid.link/20260324152935.72444-9-jonathan.cavitt@intel.com
</content>
</entry>
<entry>
<title>drm/xe/userptr: Defer Waiting for TLB invalidation to the second pass if possible</title>
<updated>2026-03-11T08:33:01+00:00</updated>
<author>
<name>Thomas Hellström</name>
<email>thomas.hellstrom@linux.intel.com</email>
</author>
<published>2026-03-05T09:39:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f7093ebf612f45544600f06681d6fb7be7d0649a'/>
<id>urn:sha1:f7093ebf612f45544600f06681d6fb7be7d0649a</id>
<content type='text'>
Now that the two-pass notifier flow uses xe_vma_userptr_do_inval() for
the fence-wait + TLB-invalidate work, extend it to support a further
deferred TLB wait:

- xe_vma_userptr_do_inval(): when the embedded finish handle is free,
  submit the TLB invalidation asynchronously (xe_vm_invalidate_vma_submit)
  and return &amp;userptr-&gt;finish so the mmu_notifier core schedules a third
  pass.  When the handle is occupied by a concurrent invalidation, fall
  back to the synchronous xe_vm_invalidate_vma() path.

- xe_vma_userptr_complete_tlb_inval(): new helper called from
  invalidate_finish when tlb_inval_submitted is set.  Waits for the
  previously submitted batch and unmaps the gpusvm pages.

xe_vma_userptr_invalidate_finish() dispatches between the two helpers
via tlb_inval_submitted, making the three possible flows explicit:

  pass1 (fences pending)  -&gt; invalidate_finish -&gt; do_inval (sync TLB)
  pass1 (fences done)     -&gt; do_inval -&gt; invalidate_finish
                          -&gt; complete_tlb_inval (deferred TLB)
  pass1 (finish occupied) -&gt; do_inval (sync TLB, inline)

In multi-GPU scenarios this allows TLB flushes to be submitted on all
GPUs in one pass before any of them are waited on.

Also adds xe_vm_invalidate_vma_submit() which submits the TLB range
invalidation without blocking, populating a xe_tlb_inval_batch that
the caller waits on separately.

v3:
- Add locking asserts and notifier state asserts (Matt Brost)
- Update the locking documentation of the notifier
  state members (Matt Brost)
- Remove unrelated code formatting changes (Matt Brost)

Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
Reviewed-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Link: https://patch.msgid.link/20260305093909.43623-5-thomas.hellstrom@linux.intel.com
</content>
</entry>
<entry>
<title>drm/xe: Split TLB invalidation into submit and wait steps</title>
<updated>2026-03-11T08:32:59+00:00</updated>
<author>
<name>Thomas Hellström</name>
<email>thomas.hellstrom@linux.intel.com</email>
</author>
<published>2026-03-05T09:39:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=400ee0f4f1f06b2c447ba87868b6da613445c31a'/>
<id>urn:sha1:400ee0f4f1f06b2c447ba87868b6da613445c31a</id>
<content type='text'>
xe_vm_range_tilemask_tlb_inval() submits TLB invalidation requests to
all GTs in a tile mask and then immediately waits for them to complete
before returning. This is fine for the existing callers, but a
subsequent patch will need to defer the wait in order to overlap TLB
invalidations across multiple VMAs.

Introduce xe_tlb_inval_range_tilemask_submit() and
xe_tlb_inval_batch_wait() in xe_tlb_inval.c as the submit and wait
halves respectively. The batch of fences is carried in the new
xe_tlb_inval_batch structure. Remove xe_vm_range_tilemask_tlb_inval()
and convert all three call sites to the new API.

v3:
- Don't wait on TLB invalidation batches if the corresponding batch
  submit returns an error. (Matt Brost)
- s/_batch/batch/ (Matt Brost)

Assisted-by: GitHub Copilot:claude-sonnet-4.6
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
Reviewed-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Link: https://patch.msgid.link/20260305093909.43623-4-thomas.hellstrom@linux.intel.com
</content>
</entry>
<entry>
<title>drm/xe/uapi: Introduce a flag to disallow vm overcommit in fault mode</title>
<updated>2026-02-24T14:27:03+00:00</updated>
<author>
<name>Thomas Hellström</name>
<email>thomas.hellstrom@linux.intel.com</email>
</author>
<published>2026-02-04T15:33:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=369cc88049855269b7620426bda4fb9ce2a2d1ca'/>
<id>urn:sha1:369cc88049855269b7620426bda4fb9ce2a2d1ca</id>
<content type='text'>
Some compute applications may try to allocate device memory to probe
how much device memory is actually available, assuming that the
application will be the only one running on the particular GPU.

That strategy fails in fault mode since it allows VM overcommit.

While this could be resolved in user-space it's further complicated
by cgroups potentially restricting the amount of memory available
to the application.

Introduce a vm create flag, DRM_XE_VM_CREATE_NO_VM_OVERCOMMIT, that
allows fault mode to mimic the behaviour of !fault mode WRT this. It
blocks evicting same vm bos during VM_BIND processing. However,
it does *not* block evicting same-vm bos during pagefault
processing, preferring eviction rather than VM banning in
OOM situations.

Cc: John Falkowski &lt;john.falkowski@intel.com&gt;
Cc: Michal Mrozek &lt;michal.mrozek@intel.com&gt;
Cc: Matthew Brost &lt;matthew.brost@intel.com&gt;
Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
Reviewed-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Link: https://patch.msgid.link/20260204153320.17989-1-thomas.hellstrom@linux.intel.com
</content>
</entry>
<entry>
<title>drm/xe: Add vm to exec queues association</title>
<updated>2026-01-17T02:24:49+00:00</updated>
<author>
<name>Matthew Brost</name>
<email>matthew.brost@intel.com</email>
</author>
<published>2026-01-16T22:17:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a3866ce7b1221353b795603bb8d0c81d81e60e65'/>
<id>urn:sha1:a3866ce7b1221353b795603bb8d0c81d81e60e65</id>
<content type='text'>
Maintain a list of exec queues per vm which will be used by TLB
invalidation code to do context-ID based tlb invalidations.

v4:
 - More asserts (Stuart)
 - Per GT list (CI)
 - Skip adding / removal if context TLB invalidatiions not supported
   (Stuart)

Signed-off-by: Nirmoy Das &lt;nirmoy.das@intel.com&gt;
Signed-off-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Reviewed-by: Stuart Summers &lt;stuart.summers@intel.com&gt;
Tested-by: Stuart Summers &lt;stuart.summers@intel.com&gt;
Link: https://patch.msgid.link/20260116221731.868657-6-matthew.brost@intel.com
</content>
</entry>
<entry>
<title>drm/xe/vm: fix xe_vm_validation_exec() kernel-doc</title>
<updated>2026-01-09T14:42:39+00:00</updated>
<author>
<name>Jani Nikula</name>
<email>jani.nikula@intel.com</email>
</author>
<published>2026-01-07T15:54:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b3a7767989e6519127ac5e0cde682c50ad587f3b'/>
<id>urn:sha1:b3a7767989e6519127ac5e0cde682c50ad587f3b</id>
<content type='text'>
Fix kernel-doc warnings on xe_vm_validation_exec():

Warning: ../drivers/gpu/drm/xe/xe_vm.h:392 expecting prototype for
  xe_vm_set_validation_exec(). Prototype was for xe_vm_validation_exec()
  instead

Fixes: 0131514f9789 ("drm/xe: Pass down drm_exec context to validation")
Cc: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
Cc: Matthew Brost &lt;matthew.brost@intel.com&gt;
Reviewed-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Link: https://patch.msgid.link/20260107155401.2379127-4-jani.nikula@intel.com
Signed-off-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe: Pass a drm_pagemap pointer around with the memory advise attributes</title>
<updated>2025-12-23T09:00:47+00:00</updated>
<author>
<name>Thomas Hellström</name>
<email>thomas.hellstrom@linux.intel.com</email>
</author>
<published>2025-12-19T11:33:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=eb9db59d96ce1ce8a207064f4a098c55ddd23fc3'/>
<id>urn:sha1:eb9db59d96ce1ce8a207064f4a098c55ddd23fc3</id>
<content type='text'>
As a consequence, struct xe_vma_mem_attr() can't simply be assigned
or freed without taking the reference count of individual members
into account. Also add helpers to do that.

v2:
- Move some calls to xe_vma_mem_attr_fini() to xe_vma_free(). (Matt Brost)
v3:
- Rebase.

Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
Reviewed-by: Matthew Brost &lt;matthew.brost@intel.com&gt; #v2
Link: https://patch.msgid.link/20251219113320.183860-13-thomas.hellstrom@linux.intel.com
</content>
</entry>
<entry>
<title>drm/xe: Add helper to extend CPU-mirrored VMA range for merge</title>
<updated>2025-11-26T10:12:33+00:00</updated>
<author>
<name>Himal Prasad Ghimiray</name>
<email>himal.prasad.ghimiray@intel.com</email>
</author>
<published>2025-11-25T07:56:24+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5b12958b1ffa7db44c276b2d394f3ddb9e0ebaca'/>
<id>urn:sha1:5b12958b1ffa7db44c276b2d394f3ddb9e0ebaca</id>
<content type='text'>
Introduce xe_vm_find_cpu_addr_mirror_vma_range(), which computes an
extended range around a given range by including adjacent VMAs that are
CPU-address-mirrored and have default memory attributes. This helper is
useful for determining mergeable range without performing the actual merge.

v2
- Add assert
- Move unmap check to this patch

v3
- Decrease offset to check by SZ_4K to avoid wrong vma return in fast
  lookup path

v4
- *start should be &gt;= SZ_4K (Matt)

Cc: Matthew Brost &lt;matthew.brost@intel.com&gt;
Cc: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
Reviewed-by: Matthew Brost &lt;matthew.brost@intel.com&gt;
Link: https://patch.msgid.link/20251125075628.1182481-2-himal.prasad.ghimiray@intel.com
Signed-off-by: Himal Prasad Ghimiray &lt;himal.prasad.ghimiray@intel.com&gt;
</content>
</entry>
<entry>
<title>drm/xe: Convert existing drm_exec transactions for exhaustive eviction</title>
<updated>2025-09-10T07:16:00+00:00</updated>
<author>
<name>Thomas Hellström</name>
<email>thomas.hellstrom@linux.intel.com</email>
</author>
<published>2025-09-08T10:12:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8f25e5abcbfb9cbcd923021774f2e785db3f7f55'/>
<id>urn:sha1:8f25e5abcbfb9cbcd923021774f2e785db3f7f55</id>
<content type='text'>
Convert existing drm_exec transactions, like GT pagefault validation,
non-LR exec() IOCTL and the rebind worker to support
exhaustive eviction using the xe_validation_guard().

v2:
- Adapt to signature change in xe_validation_guard() (Matt Brost)
- Avoid gotos from within xe_validation_guard() (Matt Brost)
- Check error return from xe_validation_guard()

v3:
- Rebase on gpu_madvise()

Signed-off-by: Thomas Hellström &lt;thomas.hellstrom@linux.intel.com&gt;
Reviewed-by: Matthew Brost &lt;matthew.brost@intel.com&gt; #v1
Link: https://lore.kernel.org/r/20250908101246.65025-6-thomas.hellstrom@linux.intel.com
</content>
</entry>
</feed>
