kernel/linux.git/drivers/gpu/drm/xe/xe_pcode_api.h, branch v7.2-rc1Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v7.2-rc12026-04-17T15:38:47+00:00drm/xe/hwmon: Read accepted power limit for CRI2026-04-17T15:38:47+00:00Karthik Poosakarthik.poosa@intel.com2026-03-23T11:58:36+00:00urn:sha1:ffc2f7fd1c2b39ef50dd92556232deec653fc466
Update xe_hwmon_pcode_read_power_limit() and
xe_hwmon_pcode_rmw_power_limit() to read the accepted power limit for
discrete platforms post CRI.
For platforms before CRI only the last written pcode value was available.
From CRI onwards, pcode exposes a new param2 value 2 that allows reading
the accepted power limit by the hardware.
v2:
- Read resolved power limit in xe_hwmon_pcode_rmw_power_limit()
as well. (Badal)
- Rephrase commit message. (Badal)
- Add prepare_power_limit_param2() to prepare param2 for mailbox power
limit read.
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>
Link: https://patch.msgid.link/20260323115836.3737300-1-karthik.poosa@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drm/xe: Add missing include guards to unprotected headers2026-04-06T15:52:53+00:00Shuicheng Linshuicheng.lin@intel.com2026-03-17T21:57:17+00:00urn:sha1:e7ac8ddfefa3729e858ac9c5a0c9af3a53d4c699
Two headers lack include guards entirely, which can cause duplicate
definition errors if they are included more than once (directly or
transitively).
Add standard _XE_<NAME>_H_ include guards to:
- xe_dep_scheduler.h: forward declarations and function prototypes
- xe_pcode_api.h: PCODE mailbox register definitions
No functional change.
Suggested-by: Nitin Gote <nitin.r.gote@intel.com>
Assisted-by: GitHub Copilot:claude-opus-4.6
Reviewed-by: Nitin Gote <nitin.r.gote@intel.com>
Link: https://patch.msgid.link/20260317215732.2208976-8-shuicheng.lin@intel.com
Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com>
drm/xe/hwmon: Expose GPU PCIe temperature2026-01-12T22:00:29+00:00Karthik Poosakarthik.poosa@intel.com2026-01-12T20:35:20+00:00urn:sha1:8d2511686ef55cfbdcc14d2f051224c3a16741d6
Expose GPU PCIe average temperature and its limits via hwmon sysfs entry
temp5_xxx.
Update Xe hwmon sysfs documentation for this.
v2: Update kernel version in Xe hwmon documentation. (Raag)
v3:
- Address review comments from Raag.
- Remove redundant debug log.
- Update kernel version in Xe hwmon documentation. (Raag)
v4:
- Address review comments from Raag.
- Group new temperature attributes with existing temperature attributes
as per channel index in Xe hwmon documentation.
- Use TEMP_MASK instead of TEMP_MASK_MAILBOX.
- Add PCIE_SENSOR_MASK which uses REG_FIELD_GET as replacement of
PCIE_SENSOR_SHIFT.
v5:
- Address review comments from Raag.
- Use REG_FIELD_GET to get PCIe temperature.
- Move PCIE_SENSOR_GROUP_ID and PCIE_SENSOR_MASK to xe_pcode_api.h
- Cosmetic change.
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Raag Jadav <raag.jadav@intel.com>
Link: https://patch.msgid.link/20260112203521.1014388-4-karthik.poosa@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drm/xe/hwmon: Expose memory controller temperature2026-01-12T22:00:29+00:00Karthik Poosakarthik.poosa@intel.com2026-01-12T20:35:19+00:00urn:sha1:3a0cb885e111db34b22058a3b82e99e49f02ac94
Expose GPU memory controller average temperature and its limits under
temp4_xxx.
Update Xe hwmon documentation for this.
v2:
- Rephrase commit message. (Badal)
- Update kernel version in Xe hwmon documentation. (Raag)
v3:
- Update kernel version in Xe hwmon documentation.
- Address review comments from Raag.
- Remove obvious comments.
- Remove redundant debug logs.
- Remove unnecessary checks.
- Avoid magic numbers.
- Add new comments.
- Use temperature sensors count to make memory controller visible.
- Use temperature limits of package for memory controller.
v4:
- Address review comments from Raag.
- Group new temperature attributes with existing temperature attributes
as per channel index in Xe hwmon documentation.
- Use DIV_ROUND_UP to calculate dwords needed for temperature limits.
- Minor aesthetic refinements.
- Remove unused TEMP_MASK_MAILBOX.
v5:
- Use REG_FIELD_GET to get count from READ_THERMAL_DATA output. (Raag)
- Change count print from decimal to hexadecimal.
- Cosmetic changes.
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Raag Jadav <raag.jadav@intel.com>
Link: https://patch.msgid.link/20260112203521.1014388-3-karthik.poosa@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drm/xe/hwmon: Expose temperature limits2026-01-12T22:00:29+00:00Karthik Poosakarthik.poosa@intel.com2026-01-12T20:35:18+00:00urn:sha1:c332fba805d659eca1f8e3a41d259c03421e81f1
Read temperature limits using pcode mailbox and expose shutdown
temperature limit as tempX_emergency, critical temperature limit as
tempX_crit and GPU max temperature limit as temp2_max.
Update Xe hwmon documentation with above entries.
v2:
- Resolve a documentation warning.
- Address below review comments from Raag.
- Update date and kernel version in Xe hwmon documentation.
- Remove explicit disable of has_mbx_thermal_info for unsupported
platforms.
- Remove unnecessary default case in switches.
- Remove obvious comments.
- Use TEMP_LIMIT_MAX to compute number of dwords needed in
xe_hwmon_thermal_info.
- Remove THERMAL_LIMITS_DWORDS macro.
- Use has_mbx_thermal_info for checking thermal mailbox support.
v3:
- Address below minor comments. (Raag)
- Group new temperature attributes with existing temperature attributes
as per channel index in Xe hwmon documentation.
- Rename enums of xe_temp_limit to improve clarity.
- Use DIV_ROUND_UP to calculate dwords needed for temperature limits.
- Use return instead of breaks in xe_hwmon_temp_read.
- Minor aesthetic refinements.
v4:
- Remove a redundant break. (Raag)
- Update drm_dbg to drm_warn to inform user of unavailability for
thermal mailbox on expected platforms.
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Raag Jadav <raag.jadav@intel.com>
Link: https://patch.msgid.link/20260112203521.1014388-2-karthik.poosa@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drm/xe/xe_survivability: Add support for survivability mode v22025-12-09T22:19:43+00:00Riana Tauroriana.tauro@intel.com2025-12-08T08:45:42+00:00urn:sha1:1987ea95ac37ea3f9299d220974676207d5262f6
v2 survivability breadcrumbs introduces a new mode called
SPI Flash Descriptor Override mode (FDO). This is enabled by
PCODE when MEI itself fails and firmware cannot be updated via
MEI using igsc. This mode provides the ability to update
the firmware directly via SPI driver.
Xe KMD initializes the nvm aux driver if FDO mode is enabled.
Userspace should check FDO mode entry in survivability info sysfs before
using the SPI driver to update firmware.
/sys/bus/pci/devices/<device>/survivability_info/fdo_mode
v2 also supports survivability mode for critical boot errors.
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20251208084539.3652902-6-riana.tauro@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drm/xe/pcode: Rework error mapping2025-11-12T16:57:27+00:00Lucas De Marchilucas.demarchi@intel.com2025-11-10T16:41:08+00:00urn:sha1:459a0ce8dcb19edbd270d26b07fc9d72bfeece36
The sparse array used for error decoding from is unnecessarily big. It
should be better handled by a switch statement that will also allow us
to more easily improve this code.
Add a CASE_ERR() macro to keep the table compact and use it instead of
the 256-entries array, which saves some space:
$ bloat-o-meter xe_pcode.o.old xe_pcode.o
add/remove: 0/1 grow/shrink: 2/0 up/down: 190/-4096 (-3906)
Function old new delta
__pcode_mailbox_rw 363 465 +102
__pcode_mailbox_rw.cold 58 146 +88
err_decode 4096 - -4096
Total: Before=7890, After=3984, chg -49.51%
Reviewed-by: Raag Jadav <raag.jadav@intel.com>
Link: https://patch.msgid.link/20251110-pcode-errmap-v2-1-cb18c8f54238@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
drm/xe: Expose fan control and voltage regulator version2025-07-09T22:25:22+00:00Raag Jadavraag.jadav@intel.com2025-07-09T16:42:24+00:00urn:sha1:cdc36b66cd41d0f6e18e86d7aa50554c852f97e2
Add sysfs attributes for late binding features which expose bound version
to the user.
v2: Rework attribute and macro naming (Badal)
v3: Drop fancy formatting (Rodrigo)
v4: Form version string using local variables (Rodrigo)
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/20250709164224.2676086-1-raag.jadav@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drm/xe/hwmon: Add support to manage power limits though mailbox2025-05-30T15:30:01+00:00Karthik Poosakarthik.poosa@intel.com2025-05-29T16:34:53+00:00urn:sha1:7596d839f6228757fe17a810da2d1c5f3305078c
Add support to manage power limits using pcode mailbox commands
for supported platforms.
v2:
- Address review comments. (Badal)
- Use mailbox commands instead of registers to manage power limits
for BMG.
- Clamp the maximum power limit to GPU firmware default value.
v3:
- Clamp power limit in write also for platforms with mailbox support.
v4:
- Remove unnecessary debug prints. (Badal)
v5:
- Update description of variable pl1_on_boot to fix kernel-doc error.
v6:
- Improve commit message, refer to BIOS as GPU firmware.
- Change macro READ_PL_FROM_BIOS to READ_PL_FROM_FW.
- Rectify drm_warn to drm_info.
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Fixes: e90f7a58e659 ("drm/xe/hwmon: Add HWMON support for BMG")
Reviewed-by: Badal Nilawar <badal.nilawar@intel.com>
Link: https://lore.kernel.org/r/20250529163458.2354509-2-karthik.poosa@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drm/xe: Expose PCIe link downgrade attributes2025-05-07T19:31:11+00:00Raag Jadavraag.jadav@intel.com2025-05-06T05:48:34+00:00urn:sha1:0e414bf7ad012e55c8a0aa4e91f68cb1cf5801ff
Expose sysfs attributes for PCIe link downgrade capability and status.
v2: Move from debugfs to sysfs (Lucas, Rodrigo, Badal)
Rework macros and their naming (Rodrigo)
v3: Use sysfs_create_files() (Riana)
Fix checkpatch warning (Riana)
v4: s/downspeed/downgrade (Lucas, Rodrigo, Riana)
v5: Use PCIe Gen agnostic naming (Rodrigo)
v6: s/pcie_gen/auto_link (Lucas)
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
Link: https://lore.kernel.org/r/20250506054835.3395220-3-raag.jadav@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>