kernel/linux.git/drivers/gpu/drm/xe/xe_pat.c, branch linux-7.0.y

drm/xe: Allow compressible surfaces to be 1-way coherent

2026-01-09T22:55:58+00:00

Previously, compressible surfaces were required to be non-coherent (allocated as WC) because compression and coherency were mutually exclusive. Starting with Xe3, hardware supports combining compression with 1-way coherency, allowing compressible surfaces to be allocated as WB memory. This provides applications with more efficient memory allocation by avoiding WC allocation overhead that can cause system stuttering and memory management challenges. The implementation adds support for compressed+coherent PAT entry for the xe3_lpg devices and updates the driver logic to handle the new compression capabilities. v2: (Matthew Auld) - Improved error handling with XE_IOCTL_DBG() - Enhanced documentation and comments - Fixed xe_bo_needs_ccs_pages() outdated compression assumptions v3: - Improve WB compression support detection by checking PAT table instead of version check v4: - Add XE_CACHE_WB_COMPRESSION, which simplifies the logic. v5: - Use U16_MAX for the invalid PAT index. (Matthew Auld) Bspec: 71582, 59361, 59399 Cc: Matthew Auld Cc: Matt Roper Signed-off-by: Xin Wang Reviewed-by: Matthew Auld Link: https://patch.msgid.link/20260109093007.546784-1-x.wang@intel.com Signed-off-by: Matt Roper

drm/xe: Optimize flushing of L2$ by skipping unnecessary page reclaim

2025-12-13T00:59:10+00:00

There are additional hardware managed L2$ flushing such as the transient display. In those scenarios, page reclamation is unnecessary resulting in redundant cacheline flushes, so skip over those corresponding ranges. v2: - Elaborated on reasoning for page reclamation skip based on Tejas's discussion. (Matthew A, Tejas) v3: - Removed MEDIA_IS_ON due to racy condition resulting in removal of relevant registers and values. (Matthew A) - Moved l3 policy access to xe_pat. (Matthew A) v4: - Updated comments based on previous change. (Tejas) - Move back PAT index macros to xe_pat.c. Signed-off-by: Brian Nguyen Reviewed-by: Tejas Upadhyay Cc: Matthew Auld Signed-off-by: Matthew Brost Link: https://patch.msgid.link/20251212213225.3564537-21-brian3.nguyen@intel.com

drm/xe: expose PAT software config to debugfs

2025-12-05T16:15:28+00:00

The existing "pat" debugfs node dumps the live PAT registers. Under SR-IOV the VF cannot touch those registers, so the file vanishes and users lose all PAT visibility. Add a VF-safe "pat_sw_config" entry to the VF-safe debugfs list. It prints the cached PAT table the driver programmed, rather than poking HW, so PF and VF instances present the same view. This lets IGT and other tools query the PAT configuration without carrying platform-specific tables or mirroring kernel logic. v2: (Jonathan) - Only append "(* = reserved entry)" to the PAT table header on Xe2+ platforms where it actually applies. - Deduplicate the PTA/ATS mode printing by introducing the small drm_printf_pat_mode() helper macro. v3: (Matt) - Print IDX[XE_CACHE_NONE_COMPRESSION] on every Xe2+ platform so the dump always reflects the value the driver might use (even if it defaults to 0) and future IP revisions don’t need extra condition tweaks. v4: - Drop the drm_printf_pat_mode macro and introduce a real helper xe2_pat_entry_dump(). (Jani) - Reuse the helper across all PTA/ATS/PAT dumps for xe2+ entries to keep output format identical. v5: (Matt) - Split the original patch into two: one for refactoring helpers, one for the new debugfs entry. CC: Jani Nikula Suggested-by: Matt Roper Signed-off-by: Xin Wang Reviewed-by: Jonathan Cavitt Signed-off-by: Matt Roper Link: https://patch.msgid.link/20251205070633.28072-1-x.wang@intel.com

drm/xe: Refactor PAT dump to use shared helpers

2025-12-05T16:15:28+00:00

Move the PAT entry formatting into shared helper functions to ensure consistency and enable code reuse. This preparation is necessary for a follow-up patch that introduces a software-based PAT dump, which is required for debugging on VFs where hardware access is limited. V2: (Matt) - Xe3p XPC doesn’t define COMP_EN; omit it to match bspec and avoid confusion. Suggested-by: Matt Roper Signed-off-by: Xin Wang Reviewed-by: Matt Roper Signed-off-by: Matt Roper Link: https://patch.msgid.link/20251205070220.27859-1-x.wang@intel.com

drm/xe/pat: Use scope-based forcewake

2025-11-19T19:58:57+00:00

Use scope-based cleanup for forcewake in the PAT code to slightly simplify the code. Reviewed-by: Gustavo Sousa Link: https://patch.msgid.link/20251118164338.3572146-37-matthew.d.roper@intel.com Signed-off-by: Matt Roper

drm/xe/pat: Add helper to query compression enable status

2025-11-14T13:47:52+00:00

Add xe_pat_index_get_comp_en() helper function to check whether compression is enabled for a given PAT index by extracting the XE2_COMP_EN bit from the PAT table entry. There are no current users, however there are multiple in-flight series which will all use this helper. CC: Nitin Gote CC: Sanjay Yadav CC: Matt Roper Suggested-by: Matthew Auld Signed-off-by: Xin Wang Reviewed-by: Matt Roper Reviewed-by: Nitin Gote Reviewed-by: Matthew Auld Reviewed-by: Sanjay Yadav Signed-off-by: Matthew Auld Link: https://patch.msgid.link/20251110221458.1864507-2-x.wang@intel.com

drm/xe: highlight reserved PAT entries in dump output

2025-10-31T15:46:55+00:00

Enhance the PAT table dump by marking reserved entries with an asterisk (*) for improved readability and debugging. V2: Added a note in the "PAT table" header explaining the meaning of the asterisk(*) to improve clarity for readers. (Matt Roper) V3: Introduced a valid field in struct xe_pat_table_entry to explicitly track whether an entry is valid or reserved, avoiding reliance on coh_mode == 0. (Matt Roper) Signed-off-by: Xin Wang Reviewed-by: Matt Roper Link: https://patch.msgid.link/20251030221734.1058350-1-x.wang@intel.com Signed-off-by: Matt Roper

drm/xe/xe3p_xpc: Setup PAT table

2025-10-19T02:45:14+00:00

Xe3p_XPC IP requires a new PAT table; note that this table has one fewer column than the Xe2/Xe3 tables since compression is not supported. There's also no "WT" entry (which we wouldn't have used on a platform without display anyway). Bspec: 71582 Signed-off-by: Matt Roper Reviewed-by: Balasubramani Vivekanandan Link: https://lore.kernel.org/r/20251016-xe3p-v3-23-3dd173a3097a@intel.com Signed-off-by: Lucas De Marchi

drm/xe/debugfs: Update xe_pat_dump signature

2025-09-30T08:21:28+00:00

Our debugfs helper xe_gt_debugfs_show_with_rpm() expects print() functions to return int. New signature allows us to drop wrapper. While around, move kernel-doc closer to the function definition, as suggested in the doc-guide. Signed-off-by: Michal Wajdeczko Cc: Rodrigo Vivi Reviewed-by: Rodrigo Vivi Link: https://lore.kernel.org/r/20250923211613.193347-6-michal.wajdeczko@intel.com

drm/xe/pat: Consolidate PAT programming logic for pre-Xe2 and post-Xe2

2025-06-16T15:58:59+00:00

Now that the PAT settings for the new special entries introduced by Xe2 are decided during early software init and left NULL on platforms they don't apply to, there's no need to keep separate programming functions for pre-Xe2 and post-Xe2 platforms. Consolidate down to a single pair of programming functions (mcr and non-mcr) that can be used on any platform. Reviewed-by: Tejas Upadhyay Link: https://lore.kernel.org/r/20250613214751.792066-4-matthew.d.roper@intel.com Signed-off-by: Matt Roper