kernel/linux.git/drivers/gpu/drm/xe/regs, branch linux-6.9.y

drm/xe: Label RING_CONTEXT_CONTROL as masked

2024-04-11T13:41:54+00:00

RING_CONTEXT_CONTROL is a masked register. v2: Also clean up setting register value (Lucas) Reviewed-by: Matt Roper Reviewed-by: Lucas De Marchi Signed-off-by: Ashutosh Dixit Link: https://patchwork.freedesktop.org/patch/msgid/20240404161256.3852502-1-ashutosh.dixit@intel.com (cherry picked from commit dc30c6e7149baaae4288c742de95212b31f07438) Signed-off-by: Lucas De Marchi

drm/xe/hwmon: Refactor xe hwmon

2024-02-06T13:42:03+00:00

Check latest platform first in xe_hwmon_get_reg. Move PVC HWMON registers to regs/xe_pcode.h. Suggested-by: Matt Roper Signed-off-by: Karthik Poosa Reviewed-by: Badal Nilawar Signed-off-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20240201180600.434822-1-karthik.poosa@intel.com

drm/xe/xe2_lpg: Introduce performance guide changes

2024-01-23T15:41:00+00:00

Add performance guide changes to Xe2_LPG. BSpec: 72161 Signed-off-by: Shekhar Chauhan Reviewed-by: Matt Roper Signed-off-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20240123050552.2250699-2-shekhar.chauhan@intel.com

drm/xe/gsc: add support for GSC proxy interrupt

2024-01-18T19:04:37+00:00

The GSC notifies us of a proxy request via the HECI2 interrupt. The interrupt must be enabled both in the HECI layer and in our usual gt irq programming; for the latter, the interrupt is enabled via the same enable register as the GSC CS, but it does have its own mask register. When the interrupt is received, we also need to de-assert it in both layers. The handling of the proxy request is deferred to the same worker that we use for GSC load. New flags have been added to distinguish between the init case and the proxy interrupt. v2: rename irq define, fix include ordering (Alan) Signed-off-by: Daniele Ceraolo Spurio Cc: Alan Previn Cc: Suraj Kandpal Reviewed-by: Alan Previn Link: https://patchwork.freedesktop.org/patch/msgid/20240117182621.2653049-3-daniele.ceraolospurio@intel.com

drm/xe/xe2_lpg: Add Wa_16018610683

2024-01-09T18:39:43+00:00

Force max 128KB SLM during WMTP PASS1 Restore. BSpec: 70202 Signed-off-by: Shekhar Chauhan Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20240109055550.679289-1-shekhar.chauhan@intel.com Signed-off-by: Matt Roper

drm/xe/xe2: synchronise CS_CHICKEN1 with WMTP support

2024-01-08T19:43:19+00:00

Recommendation is to read FUSE4 register to check if WMTP has been enabled/disabled by HW. If enabled we don't need to do anything special, however if disabled recommendation is to also disable the WMTP mode in the FF_SLICE_CS_CHICKEN2 register, falling back to thread-group and mid-batch preemption only. However on Linux, the per-context CS_CHICKEN1 is how userspace controls pre-emption, so instead use the default lrc to disable WMTP using CS_CHICKEN1, if disabled by HW. Userspace is still free to set CS_CHICKEN1 to whatever they want later. v2: remove redundant version check and also add descriptive name(Matt) v3: remove usage of REG_FIELD_GET(Matt) Cc: Matt Roper Co-developed-by: Matthew Auld Signed-off-by: Matthew Auld Signed-off-by: Nirmoy Das Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20240104182615.21327-1-nirmoy.das@intel.com Signed-off-by: Matt Roper

drm/xe/xe2: Add workaround 16020183090

2023-12-27T06:22:04+00:00

Graphics version 20.04, used in Lunar Lake, needs WA 16020183090 for steppings A*. Set ENABLE_SEMAPHORE_POLL_BIT in INSTPM(RENDER_RING_BASE) and whitelist CSBE_DEBUG_STATUS for userspace to be able to use it and complement the workaround. Cc: Haridhar Kalvala Cc: Matt Roper Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20231207175117.2334022-1-lucas.demarchi@intel.com Signed-off-by: Lucas De Marchi

drm/xe: Update definition of GT_INTR_DW

2023-12-21T21:31:29+00:00

Add bits definitions that we will be using in upcoming patch. Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20231214185955.1791-5-michal.wajdeczko@intel.com Signed-off-by: Michal Wajdeczko

drm/xe: Update LRC context layout definitions

2023-12-21T21:31:29+00:00

The new memory based interrupt processing uses additional entries in the context. Add required definitions. Bspec: 45585, 60184 Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20231214185955.1791-4-michal.wajdeczko@intel.com Signed-off-by: Michal Wajdeczko

drm/xe: Define registers used by memory based irq processing

2023-12-21T21:31:29+00:00

The RING_INT_SRC_RPT_PTR register points to a cacheline in memory to which an engine must report as source of interrupt prior to generating an interrupt to the host. The RING_INT_STATUS_RPT_PTR register points to the first cacheline of the Interrupt Status Report (ISR) page (4KB) in graphics memory to which all engines report their interrupt status. The RING_IMR register has the interrupt enables and interrupt masks for an engine. We will refer to these registers shortly. Bspec: 45963, 45964, 45965 Reviewed-by: Matt Roper Link: https://lore.kernel.org/r/20231214185955.1791-3-michal.wajdeczko@intel.com Signed-off-by: Michal Wajdeczko