Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v5.15.3 2021-09-16T16:06:51+00:00 2021-09-16T16:06:51+00:00 Dmitry Osipenko digetx@gmail.com 2021-08-17T02:01:52+00:00 urn:sha1:8a44924e1400d75db5c6fdaf199038580df4f79f All jobs are failing on Tegra20 because it doesn't use IOMMU and mapping function uses size of mapping that is zero instead of BO size, fix it. Fixes: d7c591bc1a3f ("drm/tegra: Implement new UAPI") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-09-16T16:06:50+00:00 Dmitry Osipenko digetx@gmail.com 2021-08-17T02:01:51+00:00 urn:sha1:71eabafac1eb67d590d4500eaf38177537ea6d4a Remove unused variables from tegra_crtc_update_memory_bandwidth(). Fixes: 04d5d5df9df7 ("drm/tegra: dc: Support memory bandwidth management") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-08-26T03:05:19+00:00 Dave Airlie airlied@redhat.com 2021-08-26T03:05:10+00:00 urn:sha1:571a9233fcd44309399ee273d7ce12dc49564839 drm/tegra: Changes for v5.15-rc1 The bulk of these changes is a more modern ABI that can be efficiently used on newer SoCs as well as older ones. The userspace parts for this are available here: - libdrm support: https://gitlab.freedesktop.org/tagr/drm/-/commits/drm-tegra-uabi-v8 - VAAPI driver: https://github.com/cyndis/vaapi-tegra-driver In addition, existing userspace from the grate reverse-engineering project has been updated to use this new ABI: - X11 driver: https://github.com/grate-driver/xf86-video-opentegra - 3D driver: https://github.com/grate-driver/grate Other than that, there's also support for display memory bandwidth management for various generations and a bit of cleanup. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thierry Reding <thierry.reding@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210813163616.2822355-1-thierry.reding@gmail.com 2021-08-13T10:31:07+00:00 Dmitry Osipenko digetx@gmail.com 2021-06-01T04:21:08+00:00 urn:sha1:ad85b0843ee4536593415ca890d7fb52cd7f1fbe It's useful to know the total number of underflow events and currently the debug stats are getting reset each time CRTC is being disabled. Let's account the overall number of events that doesn't get a reset. Reviewed-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-08-13T10:30:33+00:00 Dmitry Osipenko digetx@gmail.com 2021-06-01T04:21:07+00:00 urn:sha1:04d5d5df9df79f9045e76404775fc8a084aac23d Display controller (DC) performs isochronous memory transfers, and thus, has a requirement for a minimum memory bandwidth that shall be fulfilled, otherwise framebuffer data can't be fetched fast enough and this results in a DC's data-FIFO underflow that follows by a visual corruption. The Memory Controller drivers provide facility for memory bandwidth management via interconnect API. Let's wire up the interconnect API support to the DC driver in order to fix the distorted display output on T30 Ouya, T124 TK1 and other Tegra devices. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> [treding@nvidia.com: unbreak Tegra186+ display support] Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-08-10T15:04:05+00:00 Mikko Perttunen mperttunen@nvidia.com 2021-06-10T11:04:56+00:00 urn:sha1:ef531d01663a99981c4496a53f06935bead938a8 Bump driver version to 1.0.0 to allow userspace to detect availability of new interfaces. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-08-10T15:04:05+00:00 Mikko Perttunen mperttunen@nvidia.com 2021-06-10T11:04:55+00:00 urn:sha1:8cc95f3fd35e1de3495d9e2acb051162c739cd25 Add a firewall that validates jobs before submission to ensure they don't do anything they aren't allowed to do, like accessing memory they should not access. The firewall is functionality-wise a copy of the firewall already implemented in gpu/host1x. It is copied here as it makes more sense for it to live on the DRM side, as it is only needed for userspace job submissions, and generally the data it needs to do its job is easier to access here. In the future, the other implementation will be removed. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-08-10T15:04:05+00:00 Mikko Perttunen mperttunen@nvidia.com 2021-06-10T11:04:54+00:00 urn:sha1:13abe0bb15ceac2fb8e8853bd30c278426d95ad0 Implement the job submission IOCTL with a minimum feature set. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-08-10T15:04:05+00:00 Mikko Perttunen mperttunen@nvidia.com 2021-06-10T11:04:53+00:00 urn:sha1:44e961381354df6db92065be3ba2e608c1838b3e Implement new syncpoint wait UAPI. This is different from the legacy one in taking an absolute timestamp in line with modern DRM conventions. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-08-10T15:04:05+00:00 Mikko Perttunen mperttunen@nvidia.com 2021-06-10T11:04:52+00:00 urn:sha1:fc34833640a14f4d142a8462619fb6665483ead5 Implement TegraDRM IOCTLs for allocating and freeing syncpoints. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>