kernel/linux.git/drivers/gpu/drm/tegra, branch v4.2-rc2

Merge tag 'drm/tegra/for-4.2-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

2015-06-18T02:53:54+00:00

drm/tegra: Changes for v4.2-rc1 This contains a couple of mostly fixes for issues that have crept up in recent versions of linux-next. One issue is that DP AUX transactions of more than 4 bytes will access the wrong FIFO registers and hence become corrupt. Another fix is required to restore functionality of Tegra20 if using the GART. The current code expects the IOMMU aperture to be the complete 4 GiB address space, whereas the GART on Tegra20 only provides a 128 MiB aperture. One more issue with IOMMU support is that on 64-bit ARM, swiotlb is the default IOMMU implementation backing the DMA API. A side-effect of that is that when dma_map_sg() is called to flush caches (yes, this is a bit of a hack, but ARM does not provide a better API), swiotlb will immediately run out of memory because its bounce buffer is too small to make a framebuffer. Finally I've included a mostly cosmetic fix that stores register values in u32 rather than unsigned long to avoid sign-extension issues on 64- bit ARM. This is only a precaution since it hasn't caused any issues (yet). * tag 'drm/tegra/for-4.2-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: dpaux: Registers are 32-bit drm/tegra: gem: Flush pages after allocation drm/tegra: gem: Take into account IOMMU aperture drm/tegra: dpaux: Fix transfers larger than 4 bytes

drm/tegra: dpaux: Registers are 32-bit

2015-06-12T14:26:04+00:00

Use a sized unsigned 32-bit data type (u32) to store register contents. The DPAUX registers are 32 bits wide irrespective of the architecture's data width. Signed-off-by: Thierry Reding

drm/tegra: gem: Flush pages after allocation

2015-06-12T14:25:40+00:00

Pages allocated from shmemfs don't end up being cleared and flushed on ARMv7, so they must be flushed explicitly. Use the DMA mapping API for that purpose, even though it's not used for anything else. Signed-off-by: Thierry Reding

drm/tegra: gem: Take into account IOMMU aperture

2015-06-12T14:23:50+00:00

The IOMMU may not always be able to address 2 GiB of memory. On Tegra20, the GART supports 32 MiB starting at 0x58000000. Also the aperture on Tegra30 and later is in fact the full 4 GiB, rather than just 2 GiB as currently assumed. Signed-off-by: Thierry Reding

drm/tegra: dpaux: Fix transfers larger than 4 bytes

2015-06-12T14:22:46+00:00

The DPAUX read/write FIFO registers aren't sequential in the register space, causing transfers larger than 4 bytes to cause accesses to non- existing FIFO registers. Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support") Signed-off-by: Thierry Reding

drm/tegra: Don't use vblank_disable_immediate on incapable driver.

2015-05-08T10:56:34+00:00

Tegra would not only need a hardware vblank counter that increments at leading edge of vblank, but also support for instantaneous high precision vblank timestamp queries, ie. a proper implementation of dev->driver->get_vblank_timestamp(). Without these, there can be off-by-one errors during vblank disable/enable if the scanout is inside vblank at en/disable time, and additionally clients will never see any useable vblank timestamps when querying via drmWaitVblank ioctl. This would negatively affect swap scheduling under X11 and Wayland. Signed-off-by: Mario Kleiner Acked-by: Thierry Reding Signed-off-by: Dave Airlie

dma-buf: cleanup dma_buf_export() to make it easily extensible

2015-04-21T09:17:16+00:00

At present, dma_buf_export() takes a series of parameters, which makes it difficult to add any new parameters for exporters, if required. Make it simpler by moving all these parameters into a struct, and pass the struct * as parameter to dma_buf_export(). While at it, unite dma_buf_export_named() with dma_buf_export(), and change all callers accordingly. Reviewed-by: Maarten Lankhorst Reviewed-by: Daniel Thompson Acked-by: Mauro Carvalho Chehab Acked-by: Dave Airlie Signed-off-by: Sumit Semwal

Merge tag 'drm/tegra/for-4.1-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

2015-04-08T01:13:06+00:00

drm/tegra: Changes for v4.1-rc1 Perhaps the most noteworthy change in this set is the implementation of a hardware VBLANK counter using host1x syncpoints. The SOR registers can now be dumped via debugfs, which can be useful while debugging. The IOVA address space maintained by the driver can also be dumped via debugfs. Other than than, these changes are mostly cleanup work, such as making register names more consistent or removing unused code (that was left over after the atomic mode-setting conversion). There's also a fix for eDP that makes the driver cope with firmware that already initialized the display (such as the firmware on the Tegra-based Chromebooks). * tag 'drm/tegra/for-4.1-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: sor: Reset during initialization drm/tegra: gem: Return 64-bit offset for mmap(2) drm/tegra: hdmi: Name register fields consistently drm/tegra: hdmi: Resets are synchronous drm/tegra: dc: Document tegra_dc_state_setup_clock() drm/tegra: dc: Remove unused callbacks drm/tegra: dc: Remove unused function drm/tegra: dc: Use base atomic state helpers drm/atomic: Add helpers for state-subclassing drivers drm/tegra: dc: Implement hardware VBLANK counter gpu: host1x: Export host1x_syncpt_read() drm/tegra: sor: Dump registers via debugfs drm/tegra: sor: Registers are 32-bit drm/tegra: Provide debugfs file for the IOVA space drm/tegra: dc: Check for valid parent clock

drm/tegra: sor: Reset during initialization

2015-04-02T16:49:24+00:00

As there isn't a way for the firmware on the Nyan Chromebooks to hand over the display to the kernel, and the kernel isn't redoing the whole configuration at present. With this patch, the SOR is brought to a known state and we get correct display on every boot. Signed-off-by: Tomeu Vizoso Signed-off-by: Thierry Reding

drm/tegra: hdmi: Name register fields consistently

2015-04-02T16:49:23+00:00

Name the fields of the SOR_SEQ_CTL register consistently. Signed-off-by: Thierry Reding