kernel/linux.git/drivers/gpu/drm/tegra, branch v3.16.61

drm/tegra: dpaux: Fix transfers larger than 4 bytes

2015-07-15T09:01:27+00:00

commit 3c1dae0a07c651526f8e878d223a88f82caa5a50 upstream. The DPAUX read/write FIFO registers aren't sequential in the register space, causing transfers larger than 4 bytes to cause accesses to non- existing FIFO registers. Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support") Signed-off-by: Thierry Reding Signed-off-by: Luis Henriques

drm/tegra: add MODULE_DEVICE_TABLEs

2014-10-05T20:40:50+00:00

commit ef70728c7a6571a1a7115031e932b811f1740b2e upstream. When tegra-drm.ko is built as a module, these MODULE_DEVICE_TABLEs allow the module to be auto-loaded since the module will match the devices instantiated from device tree. (Notes for stable: in 3.14+, just git rm any conflicting file, since they are added in later kernels. For 3.13 and below, manual merging will be needed) Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding Signed-off-by: Greg Kroah-Hartman

drm/tegra: sor - Remove obsolete comment

2014-06-09T10:02:51+00:00

According to the DP specification the disparity of the first symbol should always be negative. It is therefore safe to assume that panels will conform to that and therefore parameterizing this field should never be necessary. Signed-off-by: Thierry Reding

drm/tegra: sor - Enable only the necessary number of lanes

2014-06-09T10:02:50+00:00

Instead of always enabling all four lanes, enable only the number probed from the link. Signed-off-by: Thierry Reding

drm/tegra: sor - Power on only the necessary lanes

2014-06-09T10:02:50+00:00

Power on only those lanes required for the specified link. Signed-off-by: Thierry Reding

drm/tegra: sor - Do not program interlaced mode registers

2014-06-09T10:02:49+00:00

Interlaced mode is currently not supported on the SOR, so don't program any associated registers. Signed-off-by: Thierry Reding

drm/tegra: sor - Do not hardcode link speed

2014-06-09T10:02:48+00:00

Use the speed probed from the link at runtime rather than relying on a hardcoded default. Signed-off-by: Thierry Reding

drm/tegra: sor - Do not hardcode number of blank symbols

2014-06-09T10:02:48+00:00

The number of HBLANK and VBLANK symbols can be computed at runtime so that they can be set appropriately depending on the video mode and DP link. These values are used by the packet generation logic to determine how many audio samples can be transferred during the blanking intervals. Signed-off-by: Thierry Reding

drm/tegra: sor - Don't hardcode link parameters

2014-06-09T10:02:47+00:00

The currently hardcoded link parameters don't work on all eDP panels, so compute the parameters at runtime depending on the mode and panel type to allow the driver to cope with a wider variety of panels. Note that the number of bits per pixel of the panel is still hardcoded, but this can be addressed in a separate patch. This is largely based on a patch by Stéphane Marchesin but the algorithm was largely rewritten to be more readable and concise. Signed-off-by: Stéphane Marchesin Signed-off-by: Thierry Reding

drm/tegra: sor - Change power down ordering

2014-06-09T10:02:47+00:00

Lanes are powered up in decreasing order. Power them down in increasing order for consistency. Signed-off-by: Stéphane Marchesin Signed-off-by: Thierry Reding