Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v6.3 2022-07-12T06:50:05+00:00 2022-07-12T06:50:05+00:00 Dave Airlie airlied@redhat.com 2022-07-12T05:50:41+00:00 urn:sha1:8daecf611258d252b3107132d0143752b2e186fc drm/tegra: Changes for v5.20-rc1 The bulk of these changes adds support for context isolation for the various supported host1x engines, as well as support for the hardware found on the new Tegra234 SoC generation. There's also a couple of fixes and cleanups. To round things off, the device tree bindings are converted to the new json-schema format that allows DTBs to be validated. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thierry Reding <thierry.reding@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220708181136.673789-1-thierry.reding@gmail.com 2022-07-08T15:01:15+00:00 Robin Murphy robin.murphy@arm.com 2022-04-11T19:49:10+00:00 urn:sha1:7ac1a36a9823a573ad23ece58007a74b8089fe16 Even though the IOVA API never actually needed it, iova.h is still carrying an include of dma-mapping.h, now solely for the sake of not breaking tegra-drm. Fix that properly. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2022-06-20T20:53:55+00:00 Ville Syrjälä ville.syrjala@linux.intel.com 2022-06-13T20:03:12+00:00 urn:sha1:90bb087f66745ca48f6f5e43df99a1212d89e712 drm_crtc.h has no need for drm_blend.h, so don't include it. Avoids useless rebuilds of the entire universe when touching drm_blend.h. Quite a few placs do currently depend on drm_blend.h without actually including it directly. All of those need to be fixed up. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220613200317.11305-4-ville.syrjala@linux.intel.com Acked-by: Sam Ravnborg <sam@ravnborg.org> Acked-by: Jani Nikula <jani.nikula@intel.com> 2022-06-20T20:53:55+00:00 Ville Syrjälä ville.syrjala@linux.intel.com 2022-06-14T09:54:49+00:00 urn:sha1:720cf96d8fecde29b72e1101f8a567a0ce99594f drm_crtc.h has no need for drm_frambuffer.h, so don't include it. Avoids useless rebuilds of the entire universe when touching drm_framebuffer.h. Quite a few placs do currently depend on drm_framebuffer.h without actually including it directly. All of those need to be fixed up. v2: Fix up msm some more v2: Deal with ingenic and shmobile as well Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220614095449.29311-1-ville.syrjala@linux.intel.com Acked-by: Sam Ravnborg <sam@ravnborg.org> Acked-by: Jani Nikula <jani.nikula@intel.com> 2022-03-01T10:13:09+00:00 Thierry Reding treding@nvidia.com 2022-01-12T08:36:29+00:00 urn:sha1:a649b133c3154f3d1d297cf85711957e61c0f070 The NV12, NV21, NV16, NV61, NV24 and NV42 formats are supported by Tegra114 and later display hardware. Add the necessary programming to allow them to be used. Note that this does not work for Tegra186 and later yet because those generations have a different display architecture that doesn't support the same formats. Signed-off-by: Thierry Reding <treding@nvidia.com> 2022-03-01T10:13:09+00:00 Thierry Reding treding@nvidia.com 2022-01-12T08:40:34+00:00 urn:sha1:28aa30b08de6f4b346f25f7c8bb5ba3739c1879c Use the correct pitch when programming the DC_WIN_PLANAR_STORAGE_UV register's PITCH_U field to ensure the correct value is used in all cases. This isn't currently causing any problems because the pitch for both U and V planes is always the same. Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-05-31T12:30:11+00:00 Thierry Reding treding@nvidia.com 2021-05-27T18:27:21+00:00 urn:sha1:ecc583e22d4689e38a528a8bf841ba1ce58edd7b Parameterize code in several places to allow scaling of windows. Note that this currently still relies on static programming of the various metering and memory pool allocation registers. This seems to work for the common cases, but may eventually need to be updated to support use-cases with multiple windows and higher bandwidth and latency requirements. Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-05-31T12:30:11+00:00 Thierry Reding treding@nvidia.com 2021-05-27T18:15:46+00:00 urn:sha1:e16efff4e5f490ce34a8c60d9ae7297dca5eb616 The driver currently exposes several YUV formats but fails to properly program all the registers needed to display such formats. Add the right programming sequences so that overlay windows can be used to accelerate color format conversions in multimedia playback use-cases. Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-05-17T10:31:05+00:00 Nathan Chancellor nathan@kernel.org 2021-04-15T15:29:14+00:00 urn:sha1:dc9a91d279b721aef7c4f1a2e2e33631d388446f Clang warns: drivers/gpu/drm/tegra/hub.c:513:11: warning: shift count >= width of type [-Wshift-count-overflow] base |= BIT(39); ^~~~~~~ BIT is unsigned long, which is 32-bit on ARCH=arm, hence the overflow warning. Switch to BIT_ULL, which is 64-bit and will not overflow. Fixes: 7b6f846785f4 ("drm/tegra: Support sector layout on Tegra194") Link: https://github.com/ClangBuiltLinux/linux/issues/1351 Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-03-31T15:42:14+00:00 Thierry Reding treding@nvidia.com 2021-03-26T14:51:39+00:00 urn:sha1:7b6f846785f41d57917e36851c120cfbe87f0809 Tegra194 has a special physical address bit that enables some memory swizzling logic to support different sector layouts. Support the bit that selects the sector layout which is passed in the framebuffer modifier. Signed-off-by: Thierry Reding <treding@nvidia.com>