Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v4.2-rc2 2015-06-12T14:40:42+00:00 2015-06-12T14:40:42+00:00 Philipp Zabel p.zabel@pengutronix.de 2015-05-20T09:34:08+00:00 urn:sha1:4946b0430c6933383d33adf101529b7085a4a682 This patch adds the bus_format field to the HSD100PXN1 panel structure. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-06-12T14:40:35+00:00 Eric Nelson eric.nelson@boundarydevices.com 2015-04-13T22:09:26+00:00 urn:sha1:c0d607e5a2b266131c7ef7aba10e0cdf50ee24c0 Add support for the Hannstar HSD100PXN1 to the DRM simple panel driver. The HSD100PXN1 is an XGA (1024x768) panel with an 18-bit LVDS interface. It supports pixel clocks in the range of 55-75 MHz. This panel is offered for sale by Freescale as a companion part to its' i.MX5x Quick Start board and i.MX6 SABRE platforms with under the name MCIMX-LVDS1. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-06-05T11:50:20+00:00 Thierry Reding treding@nvidia.com 2015-04-14T13:07:38+00:00 urn:sha1:6343f22f8255f7b77beade7c3fcb9d89d33084c7 There's some useless padding in the struct spi_driver definition. Remove it since it serves no useful purpose. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-06-05T11:49:38+00:00 Thierry Reding treding@nvidia.com 2015-04-14T13:03:26+00:00 urn:sha1:1a8f9056f59e019892c4ce192aa435c15cc37a73 Both the Samsung LD9040 and Samsung S6E8AA0 panel drivers are missing a const qualifier for their OF match tables. This data is static and never changes, so can be read-only. Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-05-22T13:02:59+00:00 Heiko Schocher hs@denx.de 2015-05-22T08:25:57+00:00 urn:sha1:dd0150026901b3fc73bd76bb423bacf5cc10393d This adds support for the LG LB070WV8 7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-04-02T17:04:15+00:00 Philipp Zabel p.zabel@pengutronix.de 2015-02-11T17:50:09+00:00 urn:sha1:1c550fa193d08920255240743f57731d4d57cd4d This adds support for the AM-800480R3TMQW-A1H 7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-04-02T17:04:14+00:00 Philipp Zabel p.zabel@pengutronix.de 2014-12-11T17:32:46+00:00 urn:sha1:ab07725abc9aa1e3dbc41ee429ad19336b31f207 The HannStar HSD070PWW1 LVDS panel data sheet lists allowed ranges additionally to the typical values for pixel clock rate (64.3-82 MHz) and blanking intervals (54-681 clock cycles horizontally, 3-23 lines vertically). This patch replaces this panel's display mode with the display timing information to describe acceptable timings. Since the HSYNC and VSYNC are unused, the distribution between front porches, back porches, and sync pulse lengths was chosen at will. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-04-02T17:04:13+00:00 Philipp Zabel p.zabel@pengutronix.de 2014-12-11T17:32:45+00:00 urn:sha1:a5d3e625148073587955bb0c49dbbba231b3234a The simple panel driver's ->get_modes() implementation calculates the display mode list from the typical timings and the ->get_timings() implementation returns the timings to the connected encoder for mode validation and fixup. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> [treding@nvidia.com: select VIDEOMODE_HELPERS] Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-04-02T17:04:12+00:00 Philipp Zabel p.zabel@pengutronix.de 2015-02-11T17:50:11+00:00 urn:sha1:725c9d40f3fe61256903adfab868f302e249fa2a This adds support for the COM43H4M85ULC 3.7" 800x480 panel to the DRM simple panel driver. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com> 2015-04-02T17:04:11+00:00 Philipp Zabel philipp.zabel@gmail.com 2015-02-11T17:50:07+00:00 urn:sha1:33536a09f02e4b179a4594fdb986dda1415339ee This patch adds the bus_format field to the GPG482739QS5 panel structure. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>