kernel/linux.git/drivers/gpu/drm/msm, branch v6.6.16

drm/msm/dsi: Enable runtime PM

2024-02-05T20:14:38+00:00

commit 6ab502bc1cf3147ea1d8540d04b83a7a4cb6d1f1 upstream. Some devices power the DSI PHY/PLL through a power rail that we model as a GENPD. Enable runtime PM to make it suspendable. Signed-off-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/543352/ Link: https://lore.kernel.org/r/20230620-topic-dsiphy_rpm-v2-2-a11a751f34f0@linaro.org Signed-off-by: Dmitry Baryshkov Signed-off-by: Amit Pundir Signed-off-by: Greg Kroah-Hartman

drm/msm/dpu: fix writeback programming for YUV cases

2024-02-05T20:14:29+00:00

[ Upstream commit 79caf2f2202b9eaad3a5a726e4b33807f67d0f1b ] For YUV cases, setting the required format bits was missed out in the register programming. Lets fix it now in preparation of adding YUV formats support for writeback. changes in v2: - dropped the fixes tag as its not a fix but adding new functionality Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/571814/ Link: https://lore.kernel.org/r/20231212205254.12422-4-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin

drm/msm/dpu: Ratelimit framedone timeout msgs

2024-02-05T20:14:29+00:00

[ Upstream commit 2b72e50c62de60ad2d6bcd86aa38d4ccbdd633f2 ] When we start getting these, we get a *lot*. So ratelimit it to not flood dmesg. Signed-off-by: Rob Clark Reviewed-by: Abhinav Kumar Reviewed-by: Marijn Suijten Patchwork: https://patchwork.freedesktop.org/patch/571584/ Link: https://lore.kernel.org/r/20231211182000.218088-1-robdclark@gmail.com Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin

drm/msm/dpu: enable writeback on SM8450

2024-02-05T20:14:29+00:00

[ Upstream commit eaa647cdbf2e357b4a14903f2f1e47ed9c4f8df3 ] Enable WB2 hardware block, enabling writeback support on this platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/570187/ Link: https://lore.kernel.org/r/20231203002743.1291956-4-dmitry.baryshkov@linaro.org Signed-off-by: Sasha Levin

drm/msm/dpu: enable writeback on SM8350

2024-02-05T20:14:28+00:00

[ Upstream commit c2949a49dfe960e952400029e14751dceff79d38 ] Enable WB2 hardware block, enabling writeback support on this platform. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/570188/ Link: https://lore.kernel.org/r/20231203002743.1291956-3-dmitry.baryshkov@linaro.org Signed-off-by: Sasha Levin

drm/msm/dp: Add DisplayPort controller for SM8650

2024-02-05T20:14:27+00:00

[ Upstream commit 1b2d98bdd7b7c64265732f5f0dace4c52c9ba8a8 ] The Qualcomm SM8650 platform comes with a DisplayPort controller with a different base offset than the previous SM8550 SoC, add support for this in the DisplayPort driver. Signed-off-by: Neil Armstrong Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/571132/ Link: https://lore.kernel.org/r/20231207-topic-sm8650-upstream-dp-v1-2-b762c06965bb@linaro.org Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin

drm/msm/dpu: Drop enable and frame_count parameters from dpu_hw_setup_misr()

2024-01-25T23:35:36+00:00

[ Upstream commit 3313c23f3eab698bc6b904520ee608fc0f7b03d0 ] Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they are always set to the same values. In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as frame_count is always set to the same value. Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util") Signed-off-by: Jessica Zhang Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/572009/ Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-2-6da6cd1bf118@quicinc.com Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin

drm/msm/dpu: Set input_sel bit for INTF

2024-01-25T23:35:36+00:00

[ Upstream commit 980fffd0c69e5df0f67ee089d405899d532aeeab ] Set the input_sel bit for encoders as it was missed in the initial implementation. Reported-by: Rob Clark Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39 Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface") Signed-off-by: Jessica Zhang Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/572007/ Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-1-6da6cd1bf118@quicinc.com Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin

drm/msm/adreno: Fix A680 chip id

2024-01-25T23:35:35+00:00

[ Upstream commit 3e6688fd96966b6c275e95c39aa367bc0a490ccd ] The only A680 referenced from DeviceTree is patch level 1, which since commit '90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GPU")' isn't a known chip id. Correct the chip id to allow the A680 to be recognized again. Fixes: 90b593ce1c9e ("drm/msm/adreno: Switch to chip-id for identifying GPU") Signed-off-by: Bjorn Andersson Patchwork: https://patchwork.freedesktop.org/patch/569839/ Signed-off-by: Rob Clark Signed-off-by: Sasha Levin

drm/msm/dpu: correct clk bit for WB2 block

2024-01-25T23:35:34+00:00

[ Upstream commit e843ca2f30e630675e2d2a75c96f4844f2854430 ] On sc7280 there are two clk bits for WB2: vbif_cli and clk_ctrl. While programming the VBIF params of WB, the driver should be toggling the former bit, while the sc7180_mdp, sc7280_mdp and sm8250_mdp structs list the latter one. Correct that to ensure proper programming sequence for WB2 on these platforms. Fixes: 255f056181ac ("drm/msm/dpu: sc7180: add missing WB2 clock control") Fixes: 3ce166380567 ("drm/msm/dpu: add writeback support for sc7280") Fixes: 53324b99bd7b ("drm/msm/dpu: add writeback blocks to the sm8250 DPU catalog") Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Tested-by: Paloma Arellano Patchwork: https://patchwork.freedesktop.org/patch/570185/ Link: https://lore.kernel.org/r/20231203002437.1291595-1-dmitry.baryshkov@linaro.org Signed-off-by: Sasha Levin