<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/msm, branch linux-5.9.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.9.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.9.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2020-10-29T09:12:16+00:00</updated>
<entry>
<title>drm/msm/a6xx: fix a potential overflow issue</title>
<updated>2020-10-29T09:12:16+00:00</updated>
<author>
<name>Zhenzhong Duan</name>
<email>zhenzhong.duan@gmail.com</email>
</author>
<published>2020-09-12T10:25:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9301245ca7473ac9811a9e03b5f415ca5810b098'/>
<id>urn:sha1:9301245ca7473ac9811a9e03b5f415ca5810b098</id>
<content type='text'>
[ Upstream commit 08d3ab4b46339bc6f97e83b54a3fb4f8bf8f4cd9 ]

It's allocating an array of a6xx_gpu_state_obj structure rathor than
its pointers.

This patch fix it.

Signed-off-by: Zhenzhong Duan &lt;zhenzhong.duan@gmail.com&gt;
Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/msm: Fix the a650 hw_apriv check</title>
<updated>2020-10-29T09:11:23+00:00</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2020-09-15T16:35:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9fdd3a243c929e0420901f89d83645275093d4dc'/>
<id>urn:sha1:9fdd3a243c929e0420901f89d83645275093d4dc</id>
<content type='text'>
[ Upstream commit e9ba8d550dd1e28870a0bdc7c11af026c2a94702 ]

Commit 604234f33658 ("drm/msm: Enable expanded apriv support for a650")
was checking the result of adreno_is_a650() before the gpu revision
got probed in adreno_gpu_init() so it was always coming across as
false. Snoop into the revision ID ahead of time to correctly set the
hw_apriv flag so that it can be used by msm_gpu to properly setup
global buffers.

Fixes: 604234f33658 ("drm/msm: Enable expanded apriv support for a650")
Reported-by: Jonathan Marek &lt;jonathan@marek.ca&gt;
Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Tested-by: Jonathan Marek &lt;jonathan@marek.ca&gt;
Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/msm/adreno: fix probe without iommu</title>
<updated>2020-10-29T09:11:20+00:00</updated>
<author>
<name>Luca Weiss</name>
<email>luca@z3ntu.xyz</email>
</author>
<published>2020-09-11T16:08:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=656cca4554068d4e000ff809cbb0cd382116ff3f'/>
<id>urn:sha1:656cca4554068d4e000ff809cbb0cd382116ff3f</id>
<content type='text'>
[ Upstream commit 0a48db562c6264da2ae8013491efd6e8dc780520 ]

The function iommu_domain_alloc returns NULL on platforms without IOMMU
such as msm8974. This resulted in PTR_ERR(-ENODEV) being assigned to
gpu-&gt;aspace so the correct code path wasn't taken.

Fixes: ccac7ce373c1 ("drm/msm: Refactor address space initialization")
Signed-off-by: Luca Weiss &lt;luca@z3ntu.xyz&gt;
Reviewed-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/msm: Avoid div-by-zero in dpu_crtc_atomic_check()</title>
<updated>2020-10-29T09:11:19+00:00</updated>
<author>
<name>Stephen Boyd</name>
<email>swboyd@chromium.org</email>
</author>
<published>2020-09-01T21:59:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=583d8e6b25abe775da68f922204a5d9bb7af4694'/>
<id>urn:sha1:583d8e6b25abe775da68f922204a5d9bb7af4694</id>
<content type='text'>
[ Upstream commit 22f760941844dbcee6ee446e1896532f6dff01ef ]

The cstate-&gt;num_mixers member is only set to a non-zero value once
dpu_encoder_virt_mode_set() is called, but the atomic check function can
be called by userspace before that. Let's avoid the div-by-zero here and
inside _dpu_crtc_setup_lm_bounds() by skipping this part of the atomic
check if dpu_encoder_virt_mode_set() hasn't been called yet. This fixes
an UBSAN warning:

 UBSAN: Undefined behaviour in drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:860:31
 division by zero
 CPU: 7 PID: 409 Comm: frecon Tainted: G S                5.4.31 #128
 Hardware name: Google Trogdor (rev0) (DT)
 Call trace:
  dump_backtrace+0x0/0x14c
  show_stack+0x20/0x2c
  dump_stack+0xa0/0xd8
  __ubsan_handle_divrem_overflow+0xec/0x110
  dpu_crtc_atomic_check+0x97c/0x9d4
  drm_atomic_helper_check_planes+0x160/0x1c8
  drm_atomic_helper_check+0x54/0xbc
  drm_atomic_check_only+0x6a8/0x880
  drm_atomic_commit+0x20/0x5c
  drm_atomic_helper_set_config+0x98/0xa0
  drm_mode_setcrtc+0x308/0x5dc
  drm_ioctl_kernel+0x9c/0x114
  drm_ioctl+0x2ac/0x4b0
  drm_compat_ioctl+0xe8/0x13c
  __arm64_compat_sys_ioctl+0x184/0x324
  el0_svc_common+0xa4/0x154
  el0_svc_compat_handler+0x

Cc: Abhinav Kumar &lt;abhinavk@codeaurora.org&gt;
Cc: Jeykumar Sankaran &lt;jsanka@codeaurora.org&gt;
Cc: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Cc: Sean Paul &lt;seanpaul@chromium.org&gt;
Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Reviewed-by: Abhinav Kumar &lt;abhinavk@codeaurora.org&gt;
Tested-by: Sai Prakash Ranjan &lt;saiprakash.ranjan@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-msm-fixes-2020-09-04' of https://gitlab.freedesktop.org/drm/msm into drm-fixes</title>
<updated>2020-09-08T04:51:16+00:00</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2020-09-08T04:51:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8052ff431a458ede2c17bec6a1717bfe5d600a8b'/>
<id>urn:sha1:8052ff431a458ede2c17bec6a1717bfe5d600a8b</id>
<content type='text'>
A few fixes for a potential RPTR corruption issue.

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;
From: Rob Clark &lt;robdclark@gmail.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/ &lt;CAF6AEGvnr6Nhz2J0sjv2G+j7iceVtaDiJDT8T88uW6jiBfOGKQ@mail.gmail.com
</content>
</entry>
<entry>
<title>drm/msm: Disable the RPTR shadow</title>
<updated>2020-09-04T19:14:15+00:00</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2020-09-04T02:03:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f6828e0c4045f03f9cf2df6c2a768102641183f4'/>
<id>urn:sha1:f6828e0c4045f03f9cf2df6c2a768102641183f4</id>
<content type='text'>
Disable the RPTR shadow across all targets. It will be selectively
re-enabled later for targets that need it.

Cc: stable@vger.kernel.org
Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
</content>
</entry>
<entry>
<title>drm/msm: Disable preemption on all 5xx targets</title>
<updated>2020-09-04T19:14:15+00:00</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2020-09-04T02:03:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7b3f3948c8b7053d771acc9f79810cc410f5e2e0'/>
<id>urn:sha1:7b3f3948c8b7053d771acc9f79810cc410f5e2e0</id>
<content type='text'>
Temporarily disable preemption on a5xx targets pending some improvements
to protect the RPTR shadow from being corrupted.

Cc: stable@vger.kernel.org
Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
</content>
</entry>
<entry>
<title>drm/msm: Enable expanded apriv support for a650</title>
<updated>2020-09-04T19:14:07+00:00</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2020-09-04T02:03:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=604234f33658cdd72f686be405a99646b397d0b3'/>
<id>urn:sha1:604234f33658cdd72f686be405a99646b397d0b3</id>
<content type='text'>
a650 supports expanded apriv support that allows us to map critical buffers
(ringbuffer and memstore) as as privileged to protect them from corruption.

Cc: stable@vger.kernel.org
Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
</content>
</entry>
<entry>
<title>drm/msm: Split the a5xx preemption record</title>
<updated>2020-09-04T19:12:56+00:00</updated>
<author>
<name>Jordan Crouse</name>
<email>jcrouse@codeaurora.org</email>
</author>
<published>2020-09-04T02:03:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=34221545d2069dc947131f42392fd4cebabe1b39'/>
<id>urn:sha1:34221545d2069dc947131f42392fd4cebabe1b39</id>
<content type='text'>
The main a5xx preemption record can be marked as privileged to
protect it from user access but the counters storage needs to be
remain unprivileged. Split the buffers and mark the critical memory
as privileged.

Cc: stable@vger.kernel.org
Signed-off-by: Jordan Crouse &lt;jcrouse@codeaurora.org&gt;
Signed-off-by: Rob Clark &lt;robdclark@chromium.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-fixes-2020-08-28' of git://anongit.freedesktop.org/drm/drm</title>
<updated>2020-08-28T16:46:48+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-08-28T16:46:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5ec06b5c0d259a8c7c4376b121b2f62dfbfe57ef'/>
<id>urn:sha1:5ec06b5c0d259a8c7c4376b121b2f62dfbfe57ef</id>
<content type='text'>
Pull drm fixes from Dave Airlie:
 "As expected a bit of an rc3 uptick, amdgpu and msm are the main ones,
  one msm patch was from the merge window, but had dependencies and we
  dropped it until the other tree had landed. Otherwise it's a couple of
  fixes for core, and etnaviv, and single i915, exynos, omap fixes.

  I'm still tracking the Sandybridge gpu relocations issue, if we don't
  see much movement I might just queue up the reverts. I'll talk to
  Daniel next week once he's back from holidays.

  core:
   - Take modeset bkl for legacy drivers

  dp_mst:
   - Allow null crtc in dp_mst

  i915:
   - Fix command parser desc matching with masks

  amdgpu:
   - Misc display fixes
   - Backlight fixes
   - MPO fix for DCN1
   - Fixes for Sienna Cichlid
   - Fixes for Navy Flounder
   - Vega SW CTF fixes
   - SMU fix for Raven
   - Fix a possible overflow in INFO ioctl
   - Gfx10 clockgating fix

  msm:
   - opp/bw scaling patch followup
   - frequency restoring fux
   - vblank in atomic commit fix
   - dpu modesetting fixes
   - fencing fix

  etnaviv:
   - scheduler interaction fix
   - gpu init regression fix

  exynos:
   - Just drop __iommu annotation to fix sparse warning

  omap:
   - locking state fix"

* tag 'drm-fixes-2020-08-28' of git://anongit.freedesktop.org/drm/drm: (41 commits)
  drm/amd/display: Fix memleak in amdgpu_dm_mode_config_init
  drm/amdgpu: disable runtime pm for navy_flounder
  drm/amd/display: Retry AUX write when fail occurs
  drm/amdgpu: Fix buffer overflow in INFO ioctl
  drm/amd/powerplay: Fix hardmins not being sent to SMU for RV
  drm/amdgpu: use MODE1 reset for navy_flounder by default
  drm/amd/pm: correct the thermal alert temperature limit settings
  drm/amdgpu: add asd fw check before loading asd
  drm/amd/display: Keep current gain when ABM disable immediately
  drm/amd/display: Fix passive dongle mistaken as active dongle in EDID emulation
  drm/amd/display: Revert HDCP disable sequence change
  drm/amd/display: Send DISPLAY_OFF after power down on boot
  drm/amdgpu/gfx10: refine mgcg setting
  drm/amd/pm: correct Vega20 swctf limit setting
  drm/amd/pm: correct Vega12 swctf limit setting
  drm/amd/pm: correct Vega10 swctf limit setting
  drm/amd/pm: set VCN pg per instances
  drm/amd/pm: enable run_btc callback for sienna_cichlid
  drivers: gpu: amd: Initialize amdgpu_dm_backlight_caps object to 0 in amdgpu_dm_update_backlight_caps
  drm/amd/display: Reject overlay plane configurations in multi-display scenarios
  ...
</content>
</entry>
</feed>
