kernel/linux.git/drivers/gpu/drm/msm/dsi, branch linux-5.11.y

drm/msm/dsi_pll_7nm: Fix variable usage for pll_lockdet_rate

2021-04-10T11:38:56+00:00

[ Upstream commit 9daaf31307856defb1070685418ce5a484ecda3a ] The PLL_LOCKDET_RATE_1 was being programmed with a hardcoded value directly, but the same value was also being specified in the dsi_pll_regs struct pll_lockdet_rate variable: let's use it! Based on 362cadf34b9f ("drm/msm/dsi_pll_10nm: Fix variable usage for pll_lockdet_rate") Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Signed-off-by: Rob Clark Signed-off-by: Sasha Levin

drm/msm/dsi: fix check-before-set in the 7nm dsi_pll code

2021-03-30T12:30:22+00:00

[ Upstream commit 3b24cdfc721a5f1098da22f9f68ff5f4a5efccc9 ] Fix setting min/max DSI PLL rate for the V4.1 7nm DSI PLL (used on sm8250). Current code checks for pll->type before it is set (as it is set in the msm_dsi_pll_init() after calling device-specific functions. Cc: Jonathan Marek Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Dmitry Baryshkov Signed-off-by: Rob Clark Signed-off-by: Sasha Levin

drm/msm/dsi: Correct io_start for MSM8994 (20nm PHY)

2021-03-04T11:15:06+00:00

[ Upstream commit 33a7808ce1aea6e2edc1af25db25928137940c02 ] The previous registers were *almost* correct, but instead of PHYs, they were pointing at DSI PLLs, resulting in the PHY id autodetection failing miserably. Fixes: dcefc117cc19 ("drm/msm/dsi: Add support for msm8x94") Signed-off-by: Konrad Dybcio Signed-off-by: Rob Clark Signed-off-by: Sasha Levin

drm/msm: dsi: Constify dsi_host_ops

2020-11-29T18:54:08+00:00

The only usage of dsi_host_ops is to assign its address to the ops field in the mipi_dsi_host struct, which is a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn Signed-off-by: Rob Clark

drm/msm/gem: Move prototypes to msm_gem.h

2020-11-05T00:00:55+00:00

Signed-off-by: Rob Clark Reviewed-by: Kristian H. Kristensen Signed-off-by: Rob Clark

drm/msm/dsi: do not try reading 28nm vco rate if it's not enabled

2020-11-05T00:00:55+00:00

Reading VCO rate for this PLL can cause boot stalls, if it is not enabled. Guard clk_hw_get_rate with a call to dsi_pll_28nm_clk_is_enabled(). Signed-off-by: Dmitry Baryshkov Signed-off-by: Rob Clark

drm/msm/dsi_phy_10nm: implement PHY disabling

2020-11-04T16:26:26+00:00

Implement phy_disable() callback to disable DSI PHY lanes and blocks when phy is not used. Signed-off-by: Dmitry Baryshkov Fixes: ff73ff194060 ("drm/msm/dsi: Populate the 10nm PHY funcs") Signed-off-by: Rob Clark

drm/msm/dsi_phy_7nm: implement PHY disabling

2020-11-04T16:26:26+00:00

Implement phy_disable() callback to disable DSI PHY lanes and blocks when phy is not used. Signed-off-by: Dmitry Baryshkov Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Rob Clark

drm/msm/dsi_pll_10nm: restore VCO rate during restore_state

2020-11-04T16:26:25+00:00

PHY disable/enable resets PLL registers to default values. Thus in addition to restoring several registers we also need to restore VCO rate settings. Signed-off-by: Dmitry Baryshkov Fixes: c6659785dfb3 ("drm/msm/dsi/pll: call vco set rate explicitly") Signed-off-by: Rob Clark

drm/msm/dsi_pll_7nm: restore VCO rate during restore_state

2020-11-04T16:26:25+00:00

PHY disable/enable resets PLL registers to default values. Thus in addition to restoring several registers we also need to restore VCO rate settings. Signed-off-by: Dmitry Baryshkov Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Rob Clark