kernel/linux.git/drivers/gpu/drm/msm/dsi/phy, branch linux-5.3.y

Merge tag 'drm-msm-next-2019-06-25' of https://gitlab.freedesktop.org/drm/msm into drm-next

2019-06-28T00:16:40+00:00

+ usual progress on cleanups + dsi vs EPROBE_DEFER fixes + msm8998 (snapdragon 835 support) + a540 gpu support (mesa support already landed) + dsi, dsi-phy support + mdp5 and dpu interconnect (bus/memory scaling) support + initial prep work for per-context pagetables (at least the parts that don't have external dependencies like iommu/arm-smmu) There is one more patch for fixing DSI cmd mode panels (part of a set of patches to get things working on nexus5), but it would be conflicty with 1cff7440a86e04a613665803b42034 in drm-next without rebasing or back-merge, and since it doesn't conflict with anything in msm-next, I think it best if Sean merges that through drm-mix-fixes instead. (In other news, I've been making some progress w/ getting efifb working properly on sdm850 laptop without horrible hacks, and drm/msm + clk stuff not totally falling over when bootloader enables display and things are already running when driver probes.. but not quite ready yet, hopefully we can post some of that for 5.4.. should help for both the sdm835 and sdm850 laptops.) Signed-off-by: Dave Airlie From: Rob Clark Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGsj3N4XzDLSDoa+4RHZ9wXObYmhcep0M3LjnRg48BeLvg@mail.gmail.com

drm/msm/phy/dsi_phy: Set pll to NULL in case initialization fails

2019-06-20T18:41:59+00:00

We have if (!phy->pll) checks scattered through the driver and if phy->pll is an error pointer, those checks will pass and bad things will happen :( Reviewed-by: Rob Clark Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/20190617200920.133104-1-sean@poorly.run

drm/msm/dsi: Add parentheses to quirks check in dsi_phy_hw_v3_0_lane_settings

2019-06-19T19:30:55+00:00

Clang warns: drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c:80:6: warning: logical not is only applied to the left hand side of this bitwise operator [-Wlogical-not-parentheses] if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) { ^ ~ drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c:80:6: note: add parentheses after the '!' to evaluate the bitwise operator first if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) { ^ ( ) drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c:80:6: note: add parentheses around left hand side expression to silence this warning if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) { ^ ( ) 1 warning generated. Add parentheses around the bitwise AND so it is evaluated first then negated. Fixes: 3dbbf8f09e83 ("drm/msm/dsi: Add old timings quirk for 10nm phy") Link: https://github.com/ClangBuiltLinux/linux/issues/547 Reported-by: kbuild test robot Reviewed-by: Jeffrey Hugo Reviewed-by: Sean Paul Signed-off-by: Nathan Chancellor Signed-off-by: Rob Clark

drm/msm/dsi: Add old timings quirk for 10nm phy

2019-06-18T20:56:43+00:00

The v3.0.0 10nm phy has two different implementations between MSM8998 and SDM845, which require different timings calculations. Unfortunately, the hardware designers did not choose to revise the version to account for this delta so implement a quirk instead. Signed-off-by: Jeffrey Hugo Signed-off-by: Rob Clark

drm/msm/dsi: Add support for MSM8998 10nm dsi phy

2019-06-18T20:56:43+00:00

The MSM8998 dsi phy is 10nm v3.0.0 like SDM845, however there appear to be minor differences such as the address space location. Signed-off-by: Jeffrey Hugo Signed-off-by: Rob Clark

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284

2019-06-05T15:36:37+00:00

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Reviewed-by: Alexios Zavras Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman

drm: msm: Use DRM_DEV_* instead of dev_*

2018-12-11T18:05:22+00:00

Use DRM_DEV_INFO/ERROR/WARN instead of dev_info/err/debug to generate drm-formatted specific log messages so that it will be easy to differentiate in case of multiple instances of driver. Signed-off-by: Mamta Shukla Signed-off-by: Rob Clark

drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY

2018-04-19T14:08:16+00:00

Currently the DSI PHY timings are hard-coded for a specific panel for the 10nm PHY. Replace this with the auto PHY timing calculator which can calculate the PHY timings for any panel. Changes in v4: - None Changes in v3: - None Changes in v2: - None Reviewed-by: Sean Paul Reviewed-by: Archit Taneja Signed-off-by: Abhinav Kumar Signed-off-by: Sean Paul Signed-off-by: Rob Clark

drm/msm/dsi: Populate the 10nm PHY funcs

2018-02-20T15:41:21+00:00

Populate the PHY ops with the downstream driver as reference. There are a couple of TODOs which need to be resolved: - The PHY timings are all hardcoded for now. This needs to be replaced with automatic calculations once we get/understand them. - There are some lane configuration registers which use a new representation between physical and logical lane mappings. For now, we've hardcoced them to follow the default mapping (i.e logical 0 -> phy 0, logical 1 -> phy 1 etc). Signed-off-by: Archit Taneja Signed-off-by: Rob Clark

drm/msm/dsi: Add skeleton 10nm PHY/PLL code

2018-02-20T15:41:20+00:00

Add new 10nm DSI PLL/PHY files that will be used on SDM845. Just populate empty pll/phy funcs for now. These will be filled up later. Signed-off-by: Archit Taneja Signed-off-by: Rob Clark