kernel/linux.git/drivers/gpu/drm/msm/dsi/phy, branch linux-5.11.y

drm/msm/dsi: Correct io_start for MSM8994 (20nm PHY)

2021-03-04T11:15:06+00:00

[ Upstream commit 33a7808ce1aea6e2edc1af25db25928137940c02 ] The previous registers were *almost* correct, but instead of PHYs, they were pointing at DSI PLLs, resulting in the PHY id autodetection failing miserably. Fixes: dcefc117cc19 ("drm/msm/dsi: Add support for msm8x94") Signed-off-by: Konrad Dybcio Signed-off-by: Rob Clark Signed-off-by: Sasha Levin

drm/msm/dsi_phy_10nm: implement PHY disabling

2020-11-04T16:26:26+00:00

Implement phy_disable() callback to disable DSI PHY lanes and blocks when phy is not used. Signed-off-by: Dmitry Baryshkov Fixes: ff73ff194060 ("drm/msm/dsi: Populate the 10nm PHY funcs") Signed-off-by: Rob Clark

drm/msm/dsi_phy_7nm: implement PHY disabling

2020-11-04T16:26:26+00:00

Implement phy_disable() callback to disable DSI PHY lanes and blocks when phy is not used. Signed-off-by: Dmitry Baryshkov Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Rob Clark

drm/msm/dsi: add support for 7nm DSI PHY/PLL

2020-09-12T16:59:58+00:00

This adds support for the 7nm ("V4") DSI PHY/PLL for sm8150 and sm8250. Implementation is based on 10nm driver, but updated based on the downstream 7nm driver. Signed-off-by: Jonathan Marek Tested-by: Dmitry Baryshkov (SM8250) Signed-off-by: Rob Clark

drm/msm/dsi: remove unused clk_pre/clk_post in msm_dsi_dphy_timing

2020-09-12T16:59:58+00:00

The clk_pre/clk_post values in shared_timings are used instead, and these are unused. Signed-off-by: Jonathan Marek Tested-by: Dmitry Baryshkov (SM8250) Signed-off-by: Rob Clark

drm/msm/dsi: Add phy configuration for SDM630/636/660

2020-07-31T13:46:17+00:00

These SoCs make use of the 14nm phy, but at different addresses than other 14nm units. Signed-off-by: Konrad Dybcio Signed-off-by: Rob Clark

drm/msm/dsi: save pll state before dsi host is powered off

2020-02-13T21:49:20+00:00

Save pll state before dsi host is powered off. Without this change some register values gets resetted. Signed-off-by: Harigovindan P Signed-off-by: Rob Clark

drm/msm/dsi: Add configuration for 28nm PLL on family B

2019-11-04T21:17:42+00:00

The 28nm PLL has a different iospace on MSM/APQ family B SoCs: add a new configuration and use it when the DT reports the "qcom,dsi-phy-28nm-hpm-fam-b" compatible. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Rob Clark

drm/msm/dsi: Implement qcom, dsi-phy-regulator-ldo-mode for 28nm PHY

2019-10-24T19:08:12+00:00

The DSI PHY regulator supports two regulator modes: LDO and DCDC. This mode can be selected using the "qcom,dsi-phy-regulator-ldo-mode" device tree property. However, at the moment only the 20nm PHY driver actually implements that option. Add a check in the 28nm PHY driver to program the registers correctly for LDO mode. Tested-by: Nikita Travkin # l8150 Signed-off-by: Stephan Gerhold Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/20191023165617.28738-1-stephan@gerhold.net

drm/msm/dsi: Remove set but not used variable 'lpx'

2019-10-10T18:42:59+00:00

Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/msm/dsi/phy/dsi_phy.c: In function msm_dsi_dphy_timing_calc_v2: drivers/gpu/drm/msm/dsi/phy/dsi_phy.c:156:17: warning: variable lpx set but not used [-Wunused-but-set-variable] drivers/gpu/drm/msm/dsi/phy/dsi_phy.c: In function msm_dsi_dphy_timing_calc_v3: drivers/gpu/drm/msm/dsi/phy/dsi_phy.c:273:17: warning: variable lpx set but not used [-Wunused-but-set-variable] 'lpx' in msm_dsi_dphy_timing_calc_v2 is not used since commit a4df68fa232e ("drm/msm/dsi: Add new method to calculate 14nm PHY timings") 'lpx' in msm_dsi_dphy_timing_calc_v3 is not used since commit f1fa7ff44056 ("drm/msm/dsi: implement auto PHY timing calculator for 10nm PHY") Reported-by: Hulk Robot Signed-off-by: zhengbin Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/1570690506-83287-4-git-send-email-zhengbin13@huawei.com