kernel/linux.git/drivers/gpu/drm/msm/dp/dp_ctrl.c, branch v6.12.80

drm/msm/dp: reset the link phy params before link training

2024-08-05T20:55:26+00:00

Before re-starting link training reset the link phy params namely the pre-emphasis and voltage swing levels otherwise the next link training begins at the previously cached levels which can result in link training failures. Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets") Reviewed-by: Dmitry Baryshkov Tested-by: Dmitry Baryshkov # SM8350-HDK Reviewed-by: Stephen Boyd Patchwork: https://patchwork.freedesktop.org/patch/605946/ Link: https://lore.kernel.org/r/20240725220450.131245-1-quic_abhinavk@quicinc.com Signed-off-by: Abhinav Kumar

drm/msm/dp: Removed fixed nvid "support"

2024-04-22T13:22:49+00:00

The "desc" member of struct dp_panel is zero-initialized during allocation and never assigned, resulting in dp_ctrl_use_fixed_nvid() never returning true. This returned boolean value is passed around but never acted upon. Perform constant propagation and remove the traces of "fixed nvid". Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Patchwork: https://patchwork.freedesktop.org/patch/585344/ Link: https://lore.kernel.org/r/20240328-msm-dp-cleanup-v2-2-a5aed9798d32@quicinc.com Signed-off-by: Dmitry Baryshkov

drm/msm/dp: allow voltage swing / pre emphasis of 3

2024-04-08T15:56:35+00:00

Both dp_link_adjust_levels() and dp_ctrl_update_vx_px() limit swing and pre-emphasis to 2, while the real maximum value for the sum of the voltage swing and pre-emphasis is 3. Fix the DP code to remove this limitation. Fixes: c943b4948b58 ("drm/msm/dp: add displayPort driver support") Signed-off-by: Dmitry Baryshkov Reviewed-by: Kuogee Hsieh Tested-by: Kuogee Hsieh Patchwork: https://patchwork.freedesktop.org/patch/577006/ Link: https://lore.kernel.org/r/20240203-dp-swing-3-v1-1-6545e1706196@linaro.org

drm/msm/dp: enable SDP and SDE periph flush update

2024-03-04T09:38:51+00:00

DP controller can be setup to operate in either SDP update flush mode or peripheral flush mode based on the DP controller hardware version. Starting in DP v1.2, the hardware documents require the use of peripheral flush mode for SDP packets such as PPS OR VSC SDP packets. In-line with this guidance, lets program the DP controller to use peripheral flush mode starting DP v1.2 Changes in v4: - Clear up that DP_MAINLINK_CTRL_FLUSH_MODE register requires the use of bits [24:23] - Modify macros DP_MAINLINK_FLUSH_MODE_UPDATE_SDP and DP_MAINLINK_FLUSH_MODE_SDP_PERIPH_UPDATE to explicitly set their values in the bits of DP_MAINLINK_CTRL_FLUSH_MODE_MASK Changes in v3: - Clear up that the DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE macro is setting bits [24:23] to a value of 3 Changes in v2: - Use the original dp_catalog_hw_revision() function to correctly check the DP HW version Signed-off-by: Paloma Arellano Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/579621/ Link: https://lore.kernel.org/r/20240222194025.25329-16-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov

drm/msm/dp: add VSC SDP support for YUV420 over DP

2024-03-04T09:38:50+00:00

Add support to pack and send the VSC SDP packet for DP. This therefore allows the transmision of format information to the sinks which is needed for YUV420 support over DP. Changes in v5: - Slightly modify use of drm_dp_vsc_sdp_pack() - Remove dp_catalog NULL checks - Modify dp_utils_pack_sdp_header() to more clearly pack the header buffer - Move dp_utils_pack_sdp_header() inside of dp_catalog_panel_send_vsc_sdp to clearly show the relationship between the header buffer and the vsc_sdp struct - Due to the last point, remove the dp_utils_pack_vsc_sdp() function and only call drm_dp_vsc_sdp_pack() in dp_panel_setup_vsc_sdp_yuv_420() Changes in v4: - Remove struct msm_dp_sdp_with_parity - Use dp_utils_pack_sdp_header() to pack the SDP header and parity bytes into a buffer - Use this buffer when writing the VSC SDP data in dp_catalog_panel_send_vsc_sdp() - Write to all of the MMSS_DP_GENERIC0 registers instead of just the ones with non-zero values Changes in v3: - Create a new struct, msm_dp_sdp_with_parity, which holds the packing information for VSC SDP - Use drm_dp_vsc_sdp_pack() to pack the data into the new msm_dp_sdp_with_parity struct instead of specifically packing for YUV420 format - Modify dp_catalog_panel_send_vsc_sdp() to send the VSC SDP data using the new msm_dp_sdp_with_parity struct Changes in v2: - Rename GENERIC0_SDPSIZE macro to GENERIC0_SDPSIZE_VALID - Remove dp_sdp from the dp_catalog struct since this data is being allocated at the point used - Create a new function in dp_utils to pack the VSC SDP data into a buffer - Create a new function that packs the SDP header bytes into a buffer. This function is made generic so that it can be utilized by dp_audio header bytes into a buffer - Create a new function in dp_utils that takes the packed buffer and writes to the DP_GENERIC0_* registers - Split the dp_catalog_panel_config_vsc_sdp() function into two to disable/enable sending VSC SDP packets - Check the DP HW version using the original useage of dp_catalog_hw_revision() and correct the version checking logic - Rename dp_panel_setup_vsc_sdp() to dp_panel_setup_vsc_sdp_yuv_420() to explicitly state that currently VSC SDP is only being set up to support YUV420 modes Signed-off-by: Paloma Arellano Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/579636/ Link: https://lore.kernel.org/r/20240222194025.25329-14-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov

drm/msm/dp: change clock related programming for YUV420 over DP

2024-03-04T09:34:21+00:00

Change all relevant DP controller related programming for YUV420 cases. Namely, change the pixel clock math to consider YUV420 and modify the MVID programming to consider YUV420. Changes in v2: - Move configuration control programming to a different commit - Slight code simplification - Add VSC SDP check when doing mode_pclk_khz division in dp_bridge_mode_valid Signed-off-by: Paloma Arellano Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/579640/ Link: https://lore.kernel.org/r/20240222194025.25329-12-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov

drm/msm/dp: program config ctrl for YUV420 over DP

2024-03-04T09:34:21+00:00

Change relevant DP controller related programming for YUV420 cases. Program the configuration control register to indicate YUV420. Changes in v2: - Create a new patch only for configuration control programming Signed-off-by: Paloma Arellano Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/579615/ Link: https://lore.kernel.org/r/20240222194025.25329-11-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov

drm/msm/dp: Fix spelling mistake "enale" -> "enable"

2024-02-19T11:39:23+00:00

There is a spelling mistake in a drm_dbg_dp message. Fix it. Signed-off-by: Colin Ian King Reviewed-by: Neil Armstrong Patchwork: https://patchwork.freedesktop.org/patch/577760/ Link: https://lore.kernel.org/r/20240212091639.2397424-1-colin.i.king@gmail.com Signed-off-by: Dmitry Baryshkov

drm/msm/dp: handle PHY directly in dp_ctrl

2024-02-11T20:38:07+00:00

There is little point in going trough dp_parser->io indirection each time the driver needs to access the PHY. Store the pointer directly in dp_ctrl_private. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Tested-by: Kuogee Hsieh Reviewed-by: Kuogee Hsieh Patchwork: https://patchwork.freedesktop.org/patch/576119/ Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-11-098d5f581dd3@linaro.org

drm/msm/dp: move phy_configure_opts to dp_ctrl

2024-02-11T20:38:07+00:00

There is little point in sharing phy configuration structure between several modules. Move it to dp_ctrl, which becomes the only submodule re-configuring the PHY. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Tested-by: Kuogee Hsieh Reviewed-by: Kuogee Hsieh Patchwork: https://patchwork.freedesktop.org/patch/576124/ Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-9-098d5f581dd3@linaro.org