kernel/linux.git/drivers/gpu/drm/i915, branch v6.11.8

drm/i915/display: Don't enable decompression on Xe2 with Tile4

2024-11-08T15:31:03+00:00

commit 4cce34b3835b6f7dc52ee2da95c96b6364bb72e5 upstream. >>From now on expect Tile4 not to be using compression Signed-off-by: Juha-Pekka Heikkila Reviewed-by: Mika Kahola Link: https://patchwork.freedesktop.org/patch/msgid/20240816115229.531671-2-juhapekka.heikkila@gmail.com Signed-off-by: Rodrigo Vivi Signed-off-by: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman

drm/i915/psr: Prevent Panel Replay if CRC calculation is enabled

2024-11-08T15:31:03+00:00

commit a8efd8ce280996fe29f2564f705e96e18da3fa62 upstream. Similarly as for PSR2 CRC calculation seems to timeout when Panel Replay is enabled. Fix this by falling back to PSR if CRC calculation is enabled. Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/2266 Signed-off-by: Jouni Högander Reviewed-by: Mika Kahola Link: https://patchwork.freedesktop.org/patch/msgid/20240819092549.1298233-1-jouni.hogander@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman

drm/i915: move rawclk from runtime to display runtime info

2024-11-08T15:31:03+00:00

commit a9556637a23311dea96f27fa3c3e5bfba0b38ae4 upstream. It's mostly about display, so move it under display. This should also fix rawclk freq initialization in the xe driver. v2: Change the init location Link: https://lore.kernel.org/r/20240819133138.147511-2-maarten.lankhorst@linux.intel.com Cc: Maarten Lankhorst Cc: Ville Syrjälä Reviewed-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/39330d09c48509e013f01fd0247a9b7c291173e2.1724144570.git.jani.nikula@intel.com Signed-off-by: Jani Nikula Signed-off-by: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman

drm/i915/pps: Disable DPLS_GATING around pps sequence

2024-11-08T15:31:03+00:00

commit c7085d08c7e53d9aef0cdd4b20798356f6f5d469 upstream. Disable bit 29 of SCLKGATE_DIS register around pps sequence when we turn panel power on. --v2 -Squash two commit together [Jani] -Use IS_DISPLAY_VER [Jani] -Fix multiline comment [Jani] --v3 -Define register in a more appropriate place [Mitul] --v4 -Register is already defined no need to define it again [Ville] -Use correct WA number (lineage no.) [Dnyaneshwar] -Fix the range on which this WA is applied [Dnyaneshwar] Bspec: 49304 Signed-off-by: Suraj Kandpal Reviewed-by: Dnyaneshwar Bhadane Link: https://patchwork.freedesktop.org/patch/msgid/20240813042807.4015214-1-suraj.kandpal@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman

drm/i915/display/dp: Compute AS SDP when vrr is also enabled

2024-11-08T15:31:03+00:00

commit eb53e5b933b9ff315087305b3dc931af3067d19c upstream. AS SDP should be computed when VRR timing generator is also enabled. Correct the compute condition to compute params of Adaptive sync SDP when VRR timing genrator is enabled along with sink support indication. --v2: Modify if condition (Jani). Fixes: b2013783c445 ("drm/i915/display: Cache adpative sync caps to use it later") Cc: Mitul Golani Cc: Arun R Murthy Cc: Jani Nikula Cc: intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal Signed-off-by: Ankit Nautiyal (added prefix drm in subject) Link: https://patchwork.freedesktop.org/patch/msgid/20240730040941.396862-1-mitulkumar.ajitkumar.golani@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman

drm/i915/dp: Clear VSC SDP during post ddi disable routine

2024-11-08T15:31:02+00:00

commit 3e307d6c28e7bc7d94b5699d0ed7fe07df6db094 upstream. Clear VSC SDP if intel_dp_set_infoframes is called from post ddi disable routine i.e with the variable of enable as false. This is to avoid an infoframes.enable mismatch issue which is caused when pipe is connected to eDp which has psr then connected to DPMST. In this case eDp's post ddi disable routine does not clear infoframes.enable VSC for the given pipe and DPMST does not recompute VSC SDP and write infoframes.enable which causes a mismatch. --v2 -Make the comment match the code [Jani] Signed-off-by: Suraj Kandpal Reviewed-by: Ankit Nautiyal Link: https://patchwork.freedesktop.org/patch/msgid/20240724163743.3668407-1-suraj.kandpal@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman

drm/i915/hdcp: Add encoder check in hdcp2_get_capability

2024-11-08T15:31:02+00:00

commit d34f4f058edf1235c103ca9c921dc54820d14d40 upstream. Add encoder check in intel_hdcp2_get_capability to avoid null pointer error. Signed-off-by: Suraj Kandpal Reviewed-by: Dnyaneshwar Bhadane Link: https://patchwork.freedesktop.org/patch/msgid/20240722064451.3610512-3-suraj.kandpal@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman

drm/i915/hdcp: Add encoder check in intel_hdcp_get_capability

2024-11-08T15:31:02+00:00

commit 31b42af516afa1e184d1a9f9dd4096c54044269a upstream. Sometimes during hotplug scenario or suspend/resume scenario encoder is not always initialized when intel_hdcp_get_capability add a check to avoid kernel null pointer dereference. Signed-off-by: Suraj Kandpal Reviewed-by: Dnyaneshwar Bhadane Link: https://patchwork.freedesktop.org/patch/msgid/20240722064451.3610512-2-suraj.kandpal@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman

drm/i915/display: WA for Re-initialize dispcnlunitt1 xosc clock

2024-11-08T15:31:02+00:00

commit 7fbad577c82c5dd6db7217855c26f51554e53d85 upstream. The dispcnlunit1_cp_xosc_clk should be de-asserted in display off and only asserted in display on. As part of this workaround, Display driver shall execute set-reset sequence at the end of the initialize sequence to ensure clk does not remain active in display OFF. --v2: - Rebase. --v3: - Correct HSD number in commit message. --v4: - Reformat commit message. - Use intel_de_rmw instead of intel_de_write --v5: - Build Fixes. WA: 15013987218 Signed-off-by: Mitul Golani Reviewed-by: Nemesa Garg Reviewed-by: Suraj Kandpal Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240708083247.2611258-1-mitulkumar.ajitkumar.golani@intel.com Signed-off-by: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman

drm/i915/display: Cache adpative sync caps to use it later

2024-11-08T15:31:02+00:00

commit b2013783c4458a1fe8b25c0b249d2e878bcf6999 upstream. Add new member to struct intel_dp to cache support of Adaptive Sync SDP capabilities and use it whenever required to avoid HW access to read capability during each atomic commit. -v2: - Squash both the patches Signed-off-by: Mitul Golani Reviewed-by: Arun R Murthy Link: https://patchwork.freedesktop.org/patch/msgid/20240704082638.2302092-2-mitulkumar.ajitkumar.golani@intel.com Signed-off-by: Rodrigo Vivi Signed-off-by: Lucas De Marchi Signed-off-by: Greg Kroah-Hartman