<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/i915/intel_pm.c, branch v6.2</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.2</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.2'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2022-11-14T19:32:34+00:00</updated>
<entry>
<title>Merge drm/drm-next into drm-intel-next</title>
<updated>2022-11-14T19:32:34+00:00</updated>
<author>
<name>Rodrigo Vivi</name>
<email>rodrigo.vivi@intel.com</email>
</author>
<published>2022-11-14T19:32:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=002c6ca75289a4ac4f6738213dd2d258704886e4'/>
<id>urn:sha1:002c6ca75289a4ac4f6738213dd2d258704886e4</id>
<content type='text'>
Catch up on 6.1-rc cycle in order to solve the intel_backlight
conflict on linux-next.

Signed-off-by: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-intel-gt-next-2022-11-03' of git://anongit.freedesktop.org/drm/drm-intel into drm-next</title>
<updated>2022-11-04T07:33:34+00:00</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2022-11-04T07:20:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=60ba8c5bd94e17ab4b024f5cecf8b48e2cf36412'/>
<id>urn:sha1:60ba8c5bd94e17ab4b024f5cecf8b48e2cf36412</id>
<content type='text'>
Driver Changes:

- Fix for #7306: [Arc A380] white flickering when using arc as a
  secondary gpu (Matt A)
- Add Wa_18017747507 for DG2 (Wayne)
- Avoid spurious WARN on DG1 due to incorrect cache_dirty flag
  (Niranjana, Matt A)
- Corrections to CS timestamp support for Gen5 and earlier (Ville)

- Fix a build error used with clang compiler on hwmon (GG)
- Improvements to LMEM handling with RPM (Anshuman, Matt A)
- Cleanups in dmabuf code (Mike)

- Selftest improvements (Matt A)

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Joonas Lahtinen &lt;joonas.lahtinen@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/Y2N11wu175p6qeEN@jlahtine-mobl.ger.corp.intel.com
</content>
</entry>
<entry>
<title>drm/i915: Use intel_crtc_needs_modeset() more</title>
<updated>2022-11-03T16:25:47+00:00</updated>
<author>
<name>Ville Syrjälä</name>
<email>ville.syrjala@linux.intel.com</email>
</author>
<published>2022-10-31T21:40:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=882ecff709b50b36128e07a6b0035f476c769f50'/>
<id>urn:sha1:882ecff709b50b36128e07a6b0035f476c769f50</id>
<content type='text'>
Prefer our own intel_crtc_needs_modeset() wrapper to
drm_atomic_crtc_needs_modeset() whenever we are dealing
with the intel_ types instead of drm_ types. Makes things
a bit neater in general.

Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20221031214037.1636-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula &lt;jani.nikula@intel.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'drm-intel-next-2022-10-28' of git://anongit.freedesktop.org/drm/drm-intel into drm-next</title>
<updated>2022-11-01T07:48:17+00:00</updated>
<author>
<name>Dave Airlie</name>
<email>airlied@redhat.com</email>
</author>
<published>2022-11-01T07:48:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f80c71f7a868958f0547240c9e5e82b19623783f'/>
<id>urn:sha1:f80c71f7a868958f0547240c9e5e82b19623783f</id>
<content type='text'>
- Hotplug code clean-up and organization (Jani, Gustavo)
- More VBT specific code clean-up, doc, organization,
  and improvements (Ville)
- More MTL enabling work (Matt, RK, Anusha, Jose)
- FBC related clean-ups and improvements (Ville)
- Removing unused sw_fence_await_reservation (Niranjana)
- Big chunch of display house clean-up (Ville)
- Many Watermark fixes and clean-ups (Ville)
- Fix device info for devices without display (Jani)
- Fix TC port PLLs after readout (Ville)
- DPLL ID clean-ups (Ville)
- Prep work for finishing (de)gamma readout (Ville)
- PSR fixes and improvements (Jouni, Jose)
- Reject excessive dotclocks early (Ville)
- DRRS related improvements (Ville)
- Simplify uncore register updates (Andrzej)
- Fix simulated GPU reset wrt. encoder HW readout (Imre)
- Add a ADL-P workaround (Jose)
- Fix clear mask in GEN7_MISCCPCTL update (Andrzej)
- Temporarily disable runtime_pm for discrete (Anshuman)
- Improve fbdev debugs (Nirmoy)
- Fix DP FRL link training status (Ankit)
- Other small display fixes (Ankit, Suraj)
- Allow panel fixed modes to have differing sync
  polarities (Ville)
- Clean up crtc state flag checks (Ville)
- Fix race conditions during DKL PHY accesses (Imre)
- Prep-work for cdclock squash and crawl modes (Anusha)
- ELD precompute and readout (Ville)

Signed-off-by: Dave Airlie &lt;airlied@redhat.com&gt;

From: Rodrigo Vivi &lt;rodrigo.vivi@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/Y1wd6ZJ8LdJpCfZL@intel.com
</content>
</entry>
<entry>
<title>drm/i915: use intel_uncore_rmw when appropriate</title>
<updated>2022-10-24T18:32:55+00:00</updated>
<author>
<name>Andrzej Hajda</name>
<email>andrzej.hajda@intel.com</email>
</author>
<published>2022-10-19T14:38:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5490c50438c6a8af849f3894a1b7d655349a7b7b'/>
<id>urn:sha1:5490c50438c6a8af849f3894a1b7d655349a7b7b</id>
<content type='text'>
This patch replaces all occurences of the form
intel_uncore_write(reg, intel_uncore_read(reg) OP val)
with intel_uncore_rmw.

Signed-off-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Reviewed-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Reviewed-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20221019143818.244339-1-andrzej.hajda@intel.com
</content>
</entry>
<entry>
<title>drm/i915: fix clear mask in GEN7_MISCCPCTL update</title>
<updated>2022-10-18T00:27:13+00:00</updated>
<author>
<name>Andrzej Hajda</name>
<email>andrzej.hajda@intel.com</email>
</author>
<published>2022-10-17T08:55:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f74354670fc6dfc2ac3fcf2ec2c4e5ae9155433c'/>
<id>urn:sha1:f74354670fc6dfc2ac3fcf2ec2c4e5ae9155433c</id>
<content type='text'>
GEN7_DOP_CLOCK_GATE_ENABLE bit should be cleared, not inverse.
The bug was introduced during conversion to intel_uncore_rmw helper.

Suggested-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Fixes: 8cee664d3eb6f8 ("drm/i915: use proper helper for register updates")
Signed-off-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Reviewed-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Signed-off-by: Lucas De Marchi &lt;lucas.demarchi@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20221017085525.3898649-1-andrzej.hajda@intel.com
</content>
</entry>
<entry>
<title>drm/i915/gt: Always use MCR functions on multicast registers</title>
<updated>2022-10-17T17:15:47+00:00</updated>
<author>
<name>Matt Roper</name>
<email>matthew.d.roper@intel.com</email>
</author>
<published>2022-10-14T23:02:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=46c507f03a46108e5a93acc06a060601ac9b83d6'/>
<id>urn:sha1:46c507f03a46108e5a93acc06a060601ac9b83d6</id>
<content type='text'>
Rather than relying on the implicit behavior of intel_uncore_*()
functions, let's always use the intel_gt_mcr_*() functions to operate on
multicast/replicated registers.

v2:
 - Add TLB invalidation registers

v3:
 - Switch more uncore operations in mmio_invalidate_full() to MCR
   operations for Xe_HP.  (Bala)

Cc: Balasubramani Vivekanandan &lt;balasubramani.vivekanandan@intel.com&gt;
Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Reviewed-by: Balasubramani Vivekanandan &lt;balasubramani.vivekanandan@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20221014230239.1023689-10-matthew.d.roper@intel.com
</content>
</entry>
<entry>
<title>drm/i915/gen8: Create separate reg definitions for new MCR registers</title>
<updated>2022-10-17T17:12:43+00:00</updated>
<author>
<name>Matt Roper</name>
<email>matthew.d.roper@intel.com</email>
</author>
<published>2022-10-14T23:02:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=dfa13f1bfc8648041da6f39ca95364f1030af3b9'/>
<id>urn:sha1:dfa13f1bfc8648041da6f39ca95364f1030af3b9</id>
<content type='text'>
Gen8 was the first time our hardware had multicast registers (or at
least the first time the multicast nature was exposed and MMIO accesses
could be steered).  There are some registers that transitioned from
singleton behavior to multicast during the gen7 -&gt; gen8 transition;
let's duplicate the register definitions for those registers in
preparation for upcoming patches that will handle MCR registers in a
special manner.

The registers adjusted are:
 * MISCCPCTL
 * SAMPLER_INSTDONE
 * ROW_INSTDONE
 * ROW_CHICKEN2
 * HALF_SLICE_CHICKEN1
 * HALF_SLICE_CHICKEN3

v2:
 - Use the gen8 version of HALF_SLICE_CHICKEN3 in GVT's gen9 engine MMIO
   list.  (Bala)
 - Update to the gen8 version of MISCCPCTL in a couple new workarounds
   that were recently added for DG2/PVC.  (Bala)

Signed-off-by: Matt Roper &lt;matthew.d.roper@intel.com&gt;
Reviewed-by: Balasubramani Vivekanandan &lt;balasubramani.vivekanandan@intel.com&gt;
Reviewed-by: Balasubramani Vivekanandan &lt;balasubramani.vivekanandan@intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20221014230239.1023689-2-matthew.d.roper@intel.com
</content>
</entry>
<entry>
<title>drm/i915: use proper helper for register updates</title>
<updated>2022-10-11T11:36:45+00:00</updated>
<author>
<name>Andrzej Hajda</name>
<email>andrzej.hajda@intel.com</email>
</author>
<published>2022-10-06T16:32:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8cee664d3eb6f80eb7ecc46b9a32214f0fe629d3'/>
<id>urn:sha1:8cee664d3eb6f80eb7ecc46b9a32214f0fe629d3</id>
<content type='text'>
There is special helper for register read/modify/write.

Signed-off-by: Andrzej Hajda &lt;andrzej.hajda@intel.com&gt;
Reviewed-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Signed-off-by: Andi Shyti &lt;andi.shyti@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20221006163200.2803722-5-andrzej.hajda@intel.com
</content>
</entry>
<entry>
<title>drm/i915: Add missing invalidate to g4x wm readout</title>
<updated>2022-09-26T14:20:09+00:00</updated>
<author>
<name>Ville Syrjälä</name>
<email>ville.syrjala@linux.intel.com</email>
</author>
<published>2022-06-22T15:54:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2d28094b26be804369fcf92315123ff07f3d4e0e'/>
<id>urn:sha1:2d28094b26be804369fcf92315123ff07f3d4e0e</id>
<content type='text'>
Let's not forget to mark the unused watermark levels as invalid
after the readout. The vlv/chv codepath has this but the g4x
didn't for some reason.

Signed-off-by: Ville Syrjälä &lt;ville.syrjala@linux.intel.com&gt;
Link: https://patchwork.freedesktop.org/patch/msgid/20220622155452.32587-6-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy &lt;stanislav.lisovskiy@intel.com&gt;
</content>
</entry>
</feed>
