kernel/linux.git/drivers/gpu/drm/i915/display/intel_atomic.c, branch linux-7.0.y

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-22T01:09:51+00:00

This was done entirely with mindless brute force, using git grep -l '\

treewide: Replace kmalloc with kmalloc_obj for non-scalar types

2026-02-21T09:02:28+00:00

This is the result of running the Coccinelle script from scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to avoid scalar types (which need careful case-by-case checking), and instead replace kmalloc-family calls that allocate struct or union object instances: Single allocations: kmalloc(sizeof(TYPE), ...) are replaced with: kmalloc_obj(TYPE, ...) Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...) are replaced with: kmalloc_objs(TYPE, COUNT, ...) Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...) are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...) (where TYPE may also be *VAR) The resulting allocations no longer return "void *", instead returning "TYPE *". Signed-off-by: Kees Cook

drm/i915/plane: rename intel_atomic_plane.[ch] to intel_plane.[ch]

2025-06-19T09:14:29+00:00

It's all atomic, no need to emphasize this. v2: Also update Documentation/gpu/i915.rst (Gustavo) Reviewed-by: Gustavo Sousa Link: https://lore.kernel.org/r/ba5f304e9fe71723191d872e6828d461e1a572bd.1750147992.git.jani.nikula@intel.com Signed-off-by: Jani Nikula

drm/i915: s/dsb_color_vblank/dsb_color

2025-05-26T07:48:16+00:00

With double buffer gamma registers in the mix, we need not wait for vblank to execute gamma writes through dsb. Before we implement that s/dsb_color_vblank/dsb_color. Signed-off-by: Chaitanya Kumar Borah Reviewed-by: Ville Syrjälä Signed-off-by: Animesh Manna Link: https://lore.kernel.org/r/20250523062041.166468-8-chaitanya.kumar.borah@intel.com

drm/i915/atomic: convert intel_atomic.c to struct intel_display

2025-03-25T09:56:12+00:00

Going forward, struct intel_display is the main display device data pointer. Convert intel_atomic.c to struct intel_display. Reviewed-by: Ville Syrjälä Link: https://lore.kernel.org/r/7ef6fe795e4e5c26ae0d546e57f64f494aaf56fc.1742554320.git.jani.nikula@intel.com Signed-off-by: Jani Nikula

drm/i915/dsb: Use DSB for plane/color management updates

2024-10-03T21:33:44+00:00

Push regular plane/color management updates to the DSB, if other constraints allow it. The first part of the sequence will go as follows: - CPU will kick off DSB0 immediately - DSB0 writes double bufferd non-arming registers - DSB0 evades the vblank - DSB0 writes double buffered arming registers If no color management updates is needed we follow that up with: - DSB0 waits for the undelayed vblank - DSB0 waits for the delayed vblank (usec wait) - DSB0 emits an interrupt which will cause the CPU to complete the commit If color management update is needed: - DSB0 will start DSB1 with wait for undelayed vblank - DSB0 will in parallel perform the force DEwake tricks - DSB1 writes single buffered LUT registers - DSB1 waits for the delayed vblank (usec wait) - DSB1 emits an interrupt which will cause the CPU to complete the commit With this sequence we don't need to increase the vblank delay to make room for register programming during vblank, which is a good thing for high refresh rate display. But I'll need to still think of some way to eliminate VRR commit completion related races under this scheme. Stuff that isn't ready for DSB yet: - modesets (potentially we could do at least the plane enabling via DSB) - fastsets - VRR - PSR - scalers - async flips Reviewed-by: Animesh Manna Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240930170415.23841-14-ville.syrjala@linux.intel.com

drm/i915: s/disable_lp_wm/disable_cxsr/

2024-09-24T07:56:11+00:00

The ilk+ disable_lp_wm boolean has the exact same role as disable_cxsr for gmch platforms. The documentation also still talks about CxSR on ilk+ even theough the way you control it has now change to involve toggling the LP watermarks. Get rid of disable_lp_wm and just use disable_cxsr for ilk+ as well. TODO: Unify even more to not have any gmch vs. ilk+ details in high level modeset code... Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240916162413.8555-7-ville.syrjala@linux.intel.com Reviewed-by: Vinod Govindapillai

drm/i915/dsb: Use chained DSBs for LUT programming

2024-08-29T11:54:03+00:00

In order to better handle the necessary DSB DEwake tricks let's switch over to using a chained DSB for the actual LUT programming. The CPU will start 'dsb_color_commit', which in turn will start the chained 'dsb_color_vblank'. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240624191032.27333-15-ville.syrjala@linux.intel.com Reviewed-by: Animesh Manna

drm/i915/dsb: s/dsb/dsb_color_vblank/

2024-08-29T11:54:03+00:00

We'll soon utilize several DSBs during the commit. To that end rename the current crtc_state->dsb to crtc_state->dsb_color_vblank to better reflect its role (color managemnent stuff programmed during vblank). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240624191032.27333-14-ville.syrjala@linux.intel.com Reviewed-by: Animesh Manna

drm/i915: drop unnecessary i915_reg.h includes

2024-05-31T12:51:18+00:00

With the register header refactoring, some of the includes of i915_reg.h have become unnecessary. Remove. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240530100747.328631-1-jani.nikula@intel.com Signed-off-by: Jani Nikula