kernel/linux.git/drivers/gpu/drm/bridge/synopsys, branch linux-6.9.y

drm: bridge: dw_hdmi: Set DRM bridge type

2024-02-16T13:48:36+00:00

The bridge type was set to default (Unknown). Set proper bridge type. With this fixed, debugfs output imx8mp looks proper. $ cat /sys/kernel/debug/dri/1/encoder-0/bridges bridge[0]: imx_hdmi_pvi_bridge_funcs [imx8mp_hdmi_pvi] type: [0] Unknown OF: /soc@0/bus@32c00000/display-bridge@32fc4000:fsl,imx8mp-hdmi-pvi ops: [0x0] bridge[1]: dw_hdmi_bridge_funcs [dw_hdmi] type: [11] HDMI-A OF: /soc@0/bus@32c00000/hdmi@32fd8000:fsl,imx8mp-hdmi ops: [0x7] detect edid hpd Signed-off-by: Alexander Stein Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20240108152514.533414-1-alexander.stein@ew.tq-group.com Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/20240108152514.533414-1-alexander.stein@ew.tq-group.com

drm: bridge: dw_hdmi: clear the EDID property and CEC address on failures

2024-02-09T08:16:10+00:00

If EDID read fails, clear the EDID property and CEC address. Signed-off-by: Jani Nikula Reviewed-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/a417ae48da6cc0dc8a9e3d929ce0c91f1e4905f1.1706038510.git.jani.nikula@intel.com

drm: bridge: dw_hdmi: switch to ->edid_read callback

2024-02-09T08:16:07+00:00

Prefer using the struct drm_edid based callback and functions. v2: Fix -Wuninitialized (kernel test robot) Signed-off-by: Jani Nikula Reviewed-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/400bfdeca4fd25b7624286e5969c4b0b1331c2b4.1706038510.git.jani.nikula@intel.com

Merge drm/drm-next into drm-misc-next

2024-01-29T13:20:23+00:00

Kickstart 6.9 development cycle. Signed-off-by: Maxime Ripard

drm: remove I2C_CLASS_DDC support

2024-01-18T20:10:41+00:00

After removal of the legacy EEPROM driver and I2C_CLASS_DDC support in olpc_dcon there's no i2c client driver left supporting I2C_CLASS_DDC. Class-based device auto-detection is a legacy mechanism and shouldn't be used in new code. So we can remove this class completely now. Acked-by: Alex Deucher Acked-by: Dmitry Baryshkov Acked-by: Harry Wentland Acked-by: Heiko Stuebner Acked-by: Jani Nikula Acked-by: Jernej Skrabec Reviewed-by: Thomas Zimmermann Reviewed-by: Andi Shyti Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Neil Armstrong Signed-off-by: Heiner Kallweit Signed-off-by: Wolfram Sang

ASoC: hdmi-codec: drop drm/drm_edid.h include

2024-01-16T14:07:28+00:00

hdmi-codec.h does not appear to directly need drm/drm_edid.h for anything. Remove it. There are some files that get drm/drm_edid.h by proxy; include it where needed. v2-v4: Fix build (kernel test robot ) Cc: Rob Clark Cc: Abhinav Kumar Cc: Dmitry Baryshkov Cc: Sean Paul Cc: Marijn Suijten Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Cc: Andrzej Hajda Cc: Neil Armstrong Cc: Robert Foss Cc: Laurent Pinchart Cc: Jonas Karlman Cc: Jernej Skrabec Cc: Jaroslav Kysela Cc: Takashi Iwai Cc: linux-sound@vger.kernel.org Acked-by: Maxime Ripard Reviewed-by: Andi Shyti Acked-by: Alex Deucher Reviewed-by: Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20240104201632.1100753-3-jani.nikula@intel.com

drm/bridge: synopsys: dw-mipi-dsi: Fix hcomponent lbcc for burst mode

2023-10-24T18:35:11+00:00

In order to support burst mode, vendor drivers set lane_mbps higher than bandwidth through DPI interface. So, calculate horizontal component lane byte clock cycle(lbcc) based on lane_mbps instead of pixel clock rate for burst mode. Fixes: ac87d23694f4 ("drm/bridge: synopsys: dw-mipi-dsi: Use pixel clock rate to calculate lbcc") Reported-by: Heiko Stübner Closes: https://lore.kernel.org/linux-arm-kernel/5979575.UjTJXf6HLC@diego/T/#u Tested-by: Heiko Stübner # px30 minievb with xinpeng xpp055c272 Signed-off-by: Liu Ying Signed-off-by: Heiko Stuebner Link: https://patchwork.freedesktop.org/patch/msgid/20231018035212.1778767-1-victor.liu@nxp.com

drm/bridge: synopsys: dw-mipi-dsi: Disable HSTX and LPRX timeout check

2023-10-16T09:38:45+00:00

According to Synopsys DW MIPI DSI host databook, HSTX and LPRX timeout contention detections are measured in TO_CLK_DIVISION cycles. However, the current driver programs magic values to TO_CLK_DIVISION, HSTX_TO_CNT and LPRX_TO_CNT register fields, which makes timeout error event wrongly happen for some video modes, at least for the typical 1920x1080p@60 video mode read from a HDMI monitor driven by ADV7535 DSI to HDMI bridge. While at it, the current driver doesn't enable interrupt to handle or complain about the error status, so true error just happens silently except for display distortions by visual check. Disable the timeout check by setting those timeout register fields to zero for now until someone comes along with better computations for the timeout values. Although the databook doesn't mention what happens when they are set to zero, it turns out the false error doesn't happen for the 1920x1080p@60 video mode at least. Signed-off-by: Liu Ying Reviewed-by: Neil Armstrong Signed-off-by: Robert Foss Link: https://patchwork.freedesktop.org/patch/msgid/20230821034008.3876938-8-victor.liu@nxp.com

drm/bridge: synopsys: dw-mipi-dsi: Set minimum lane byte clock cycles for HSA and HBP

2023-10-16T09:38:44+00:00

According to Synopsys support channel, each region of HSA, HBP and HFP must have minimum number of 10 bytes where constant 4 bytes are for HSS or HSE and 6 bytes are for blanking packet(header + CRC). Hence, the below table comes in. +------------+----------+-------+ | data lanes | min lbcc | bytes | +------------+----------+-------+ | 1 | 10 | 1*10 | +------------+----------+-------+ | 2 | 5 | 2*5 | +------------+----------+-------+ | 3 | 4 | 3*4 | +------------+----------+-------+ | 4 | 3 | 4*3 | +------------+----------+-------+ Implement the minimum lbcc numbers to make sure that the values programmed into DSI_VID_HSA_TIME and DSI_VID_HBP_TIME registers meet the minimum number requirement. For DSI_VID_HLINE_TIME register, it seems that the value programmed should be based on mode->htotal as-is, instead of sum up HSA, HBP, HFP and HDISPLAY. This helps the case where Raydium RM67191 DSI panel is connected, since it's video timing for hsync length is only 2 pixels and without this patch the programmed value for DSI_VID_HSA_TIME is only 2 with 4 data lanes. Signed-off-by: Liu Ying Reviewed-by: Neil Armstrong Signed-off-by: Robert Foss Link: https://patchwork.freedesktop.org/patch/msgid/20230821034008.3876938-7-victor.liu@nxp.com

drm/bridge: synopsys: dw-mipi-dsi: Use pixel clock rate to calculate lbcc

2023-10-16T09:38:43+00:00

To get better accuration, use pixel clock rate to calculate lbcc instead of lane_mbps since the pixel clock rate is in KHz while lane_mbps is in MHz. Without this, distorted image can be seen on a HDMI monitor connected with i.MX93 11x11 EVK through ADV7535 DSI to HDMI bridge in 1920x1080p@60 video mode. Signed-off-by: Liu Ying Reviewed-by: Neil Armstrong Signed-off-by: Robert Foss Link: https://patchwork.freedesktop.org/patch/msgid/20230821034008.3876938-6-victor.liu@nxp.com