kernel/linux.git/drivers/gpu/drm/bridge/analogix, branch linux-4.7.y

drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time

2016-04-05T02:13:10+00:00

It may caused a dead lock if we flush the hpd work in bridge disable time. The normal flow would like: IN --> DRM IOCTL 1. Acquire crtc_ww_class_mutex (DRM IOCTL) IN --> analogix_dp_bridge 2. Acquire hpd work lock (Flush hpd work) 3. HPD work already in idle, no need to run the work function. OUT <-- analogix_dp_bridge OUT <-- DRM IOCTL The dead lock flow would like: IN --> DRM IOCTL 1. Acquire crtc_ww_class_mutex (DRM IOCTL) IN --> analogix_dp_bridge 2. Acquire hpd work lock (Flush hpd work) IN --> analogix_dp_hotplug IN --> drm_helper_hpd_irq_event 3. Acquire mode_config lock (This lock already have been acquired in previous step 1) ** Dead Lock Now ** It's wrong to flush the hpd work in bridge->disable time, I guess the original code just want to ensure the delay work must be finish before encoder disabled. The flush work in bridge disable time is try to ensure the HPD event won't be missed before display card disabled, actually we can take a fast respond way(interrupt thread) to update DRM HPD event to fix the delay update and possible dead lock. Tested-by: Caesar Wang Tested-by: Douglas Anderson Tested-by: Heiko Stuebner Tested-by: Javier Martinez Canillas Signed-off-by: Yakir Yang

drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time

2016-04-05T02:13:10+00:00

Turn off the panel power in suspend time would help to reduce power waste. Tested-by: Caesar Wang Tested-by: Douglas Anderson Tested-by: Heiko Stuebner Tested-by: Javier Martinez Canillas Signed-off-by: Yakir Yang

drm: bridge: analogix/dp: add edid modes parse in get_modes method

2016-04-05T02:13:09+00:00

Display Port monitor could support kinds of mode which indicate in monitor edid, not just one single display resolution which defined in panel or devivetree property display timing. Note: Gustavo Padovan try to remove the controller and phy power on function in bind time at bellow commit: drm/exynos: do not start enabling DP at bind() phase But for now driver need to read edid message in .get_modes() function, so controller must be inited in bind time, so we need to add controller init back. Tested-by: Caesar Wang Tested-by: Douglas Anderson Tested-by: Heiko Stuebner Tested-by: Javier Martinez Canillas Signed-off-by: Yakir Yang

drm: bridge: analogix/dp: move hpd detect to connector detect function

2016-04-05T02:13:08+00:00

This change just make a little clean to make code more like drm core expect, move hdp detect code from bridge->enable(), and place them into connector->detect(). Note: Gustavo Padovan try to remove the controller and phy power on function in bind time at bellow commit: drm/exynos: do not start enabling DP at bind() phase But for now the connector status don't hardcode to connected, need to operate dp phy in .detect function, so we need to revert parts if Gustavo Padovan's changes, add phy poweron function in bind time. Tested-by: Caesar Wang Tested-by: Douglas Anderson Tested-by: Heiko Stuebner Tested-by: Javier Martinez Canillas Signed-off-by: Yakir Yang

drm: bridge: analogix/dp: try force hpd after plug in lookup failed

2016-04-05T02:13:07+00:00

Some edp screen do not have hpd signal, so we can't just return failed when hpd plug in detect failed. This is an hardware property, so we need add a devicetree property "analogix,need-force-hpd" to indicate this sutiation. Acked-by: Rob Herring Tested-by: Caesar Wang Tested-by: Douglas Anderson Tested-by: Heiko Stuebner Tested-by: Javier Martinez Canillas Signed-off-by: Yakir Yang

drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288

2016-04-05T02:13:07+00:00

There are some IP limit on rk3288 that only support 4 physical lanes of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag. Tested-by: Caesar Wang Tested-by: Douglas Anderson Tested-by: Heiko Stuebner Signed-off-by: Yakir Yang

drm: bridge: analogix/dp: add some rk3288 special registers setting

2016-04-05T02:13:06+00:00

RK3288 need some special registers setting, we can separate them out by the dev_type of plat_data. Tested-by: Caesar Wang Tested-by: Douglas Anderson Tested-by: Heiko Stuebner Signed-off-by: Yakir Yang

drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range

2016-04-05T02:13:02+00:00

Both hsync/vsync polarity and interlace mode can be parsed from drm display mode, and dynamic_range and ycbcr_coeff can be judge by the video code. But presumably Exynos still relies on the DT properties, so take good use of mode_fixup() in to achieve the compatibility hacks. Reviewed-by: Krzysztof Kozlowski Tested-by: Caesar Wang Tested-by: Douglas Anderson Tested-by: Heiko Stuebner Tested-by: Javier Martinez Canillas Signed-off-by: Yakir Yang

drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count

2016-04-05T02:13:02+00:00

link_rate and lane_count already configured in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}. Tested-by: Caesar Wang Tested-by: Douglas Anderson Tested-by: Heiko Stuebner Tested-by: Javier Martinez Canillas Signed-off-by: Yakir Yang

drm: bridge: analogix/dp: fix some obvious code style

2016-04-05T02:13:01+00:00

Fix some obvious alignment problems, like alignment and line over 80 characters problems, make this easy to be maintained later. Acked-by: Jingoo Han Reviewed-by: Krzysztof Kozlowski Tested-by: Caesar Wang Tested-by: Douglas Anderson Tested-by: Heiko Stuebner Tested-by: Javier Martinez Canillas Signed-off-by: Yakir Yang