kernel/linux.git/drivers/gpu/drm/amd, branch v5.9.10

drm/amd/display: Add missing pflip irq

2020-11-18T18:22:29+00:00

commit a422490a595600659664901b609aacccdbba4a5f upstream. If we have more than 4 displays we will run into dummy irq calls or flip timout issues. Signed-off-by: Bhawanpreet Lakha Reviewed-by: Charlene Liu Acked-by: Qingqing Zhuo Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 5.9.x Signed-off-by: Greg Kroah-Hartman

amd/amdgpu: Disable VCN DPG mode for Picasso

2020-11-18T18:22:14+00:00

[ Upstream commit c6d2b0fbb893d5c7dda405aa0e7bcbecf1c75f98 ] Concurrent operation of VCN and JPEG decoder in DPG mode is causing ring timeout due to power state. Signed-off-by: Veerabadhran Gopalakrishnan Reviewed-by: Leo Liu Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/pm: do not use ixFEATURE_STATUS for checking smc running

2020-11-18T18:22:11+00:00

[ Upstream commit 786436b453001dafe81025389f96bf9dac1e9690 ] This reverts commit f87812284172a9809820d10143b573d833cd3f75 ("drm/amdgpu: Fix bug where DPM is not enabled after hibernate and resume"). It was intended to fix Hawaii S4(hibernation) issue but break S3. As ixFEATURE_STATUS is filled with garbage data on resume which can be only cleared by reloading smc firmware(but that will involve many changes). So, we will revert this S4 fix and seek a new way. Signed-off-by: Evan Quan Tested-by: Sandeep Raghuraman Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/pm: perform SMC reset on suspend/hibernation

2020-11-18T18:22:11+00:00

[ Upstream commit 277b080f98803cb73a83fb234f0be83a10e63958 ] So that the succeeding resume can be performed based on a clean state. Signed-off-by: Evan Quan Tested-by: Sandeep Raghuraman Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/pm: correct the baco reset sequence for CI ASICs

2020-11-18T18:22:11+00:00

[ Upstream commit c108725ef589af462be6b957f63c7925e38213eb ] Correct some registers bitmasks and add mmBIOS_SCRATCH_7 reset. Signed-off-by: Evan Quan Tested-by: Sandeep Raghuraman Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amdgpu: perform srbm soft reset always on SDMA resume

2020-11-18T18:22:11+00:00

[ Upstream commit 253475c455eb5f8da34faa1af92709e7bb414624 ] This can address the random SDMA hang after pci config reset seen on Hawaii. Signed-off-by: Evan Quan Tested-by: Sandeep Raghuraman Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: adding ddc_gpio_vga_reg_list to ddc reg def'ns

2020-11-10T11:39:06+00:00

[ Upstream commit a1d2afc5dde29a943d32bf92eb0408c9f19541fc ] why: oem-related ddc read/write fails without these regs how: copy from hw_factory_dcn20.c Signed-off-by: Martin Leung Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amd/display: Fixed panic during seamless boot.

2020-11-10T11:39:05+00:00

[ Upstream commit 866e09f0110c6e86071954033e3067975946592a ] [why] get_pixel_clk_frequency_100hz is undefined in clock_source_funcs. [how] set function pointer: ".get_pixel_clk_frequency_100hz = get_pixel_clk_frequency_100hz" Signed-off-by: David Galiffi Reviewed-by: Bhawanpreet Lakha Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amdgpu: add DID for navi10 blockchain SKU

2020-11-10T11:39:05+00:00

[ Upstream commit 8942881144a7365143f196f5eafed24783a424a3 ] Reviewed-by: Alex Deucher Reviewed-by: Guchun Chen Signed-off-by: Tianci.Yin Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amdgpu: disable DCN and VCN for navi10 blockchain SKU(v3)

2020-11-10T11:39:05+00:00

[ Upstream commit a305e7dc5fa86ff9cf6cd2da30215a92d43c9285 ] The blockchain SKU has no display and video support, remove them. Reviewed-by: Alex Deucher Signed-off-by: Tianci.Yin Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin