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<title>kernel/linux.git/drivers/gpu/drm/amd/pm/inc, branch v6.6.134</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.134</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.134'/>
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<updated>2026-03-25T10:06:00+00:00</updated>
<entry>
<title>drm/amd/pm: Use pm_display_cfg in legacy DPM (v2)</title>
<updated>2026-03-25T10:06:00+00:00</updated>
<author>
<name>Timur Kristóf</name>
<email>timur.kristof@gmail.com</email>
</author>
<published>2025-09-09T14:17:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=da249eb3206c4bab2cad14b00325009b9b65eb2c'/>
<id>urn:sha1:da249eb3206c4bab2cad14b00325009b9b65eb2c</id>
<content type='text'>
commit 9d73b107a61b73e7101d4b728ddac3d2c77db111 upstream.

This commit is necessary for DC to function well with chips
that use the legacy power management code, ie. SI and KV.
Communicate display information from DC to the legacy PM code.

Currently DC uses pm_display_cfg to communicate power management
requirements from the display code to the DPM code.
However, the legacy (non-DC) code path used different fields
and therefore could not take into account anything from DC.

Change the legacy display code to fill the same pm_display_cfg
struct as DC and use the same in the legacy DPM code.

To ease review and reduce churn, this commit does not yet
delete the now unneeded code, that is done in the next commit.

v2:
Rebase.
Fix single_display in amdgpu_dpm_pick_power_state.

Signed-off-by: Timur Kristóf &lt;timur.kristof@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Rosen Penev &lt;rosenp@gmail.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: open brace '{' following struct go on the same line</title>
<updated>2023-07-25T17:44:00+00:00</updated>
<author>
<name>Ran Sun</name>
<email>sunran001@208suo.com</email>
</author>
<published>2023-07-21T03:32:06+00:00</published>
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<id>urn:sha1:2b048fa0ddc4021ce460c4faf96cecf63b425c5d</id>
<content type='text'>
ERROR: open brace '{' following struct go on the same line

Signed-off-by: Ran Sun &lt;sunran001@208suo.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: open brace '{' following struct go on the same line</title>
<updated>2023-07-25T17:43:56+00:00</updated>
<author>
<name>Ran Sun</name>
<email>sunran001@208suo.com</email>
</author>
<published>2023-07-21T03:27:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4a0abebd742ee5e932730fa5ba244125ccc5f2bb'/>
<id>urn:sha1:4a0abebd742ee5e932730fa5ba244125ccc5f2bb</id>
<content type='text'>
ERROR: open brace '{' following struct go on the same line

Signed-off-by: Ran Sun &lt;sunran001@208suo.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: expose swctf threshold setting for legacy powerplay</title>
<updated>2023-06-30T17:12:16+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2023-05-25T02:30:39+00:00</published>
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<id>urn:sha1:064329c595da56eff6d7a7e7760660c726433139</id>
<content type='text'>
Preparation for coming optimization which eliminates the influence of
GPU temperature momentary fluctuation.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pm: update SMU13 header files for coming OD support</title>
<updated>2023-06-09T16:36:14+00:00</updated>
<author>
<name>Evan Quan</name>
<email>evan.quan@amd.com</email>
</author>
<published>2023-04-11T03:25:52+00:00</published>
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<id>urn:sha1:a37d23f816b18a324c24d066d5bc453308913bf9</id>
<content type='text'>
Correct the data structures for OD feature support.

Signed-off-by: Evan Quan &lt;evan.quan@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: added a sysfs interface for thermal throttling</title>
<updated>2023-02-23T22:36:00+00:00</updated>
<author>
<name>Kun Liu</name>
<email>Kun.Liu2@amd.com</email>
</author>
<published>2023-02-21T08:31:18+00:00</published>
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<id>urn:sha1:c3ed0e72c872901659ed0fef4b91eb6ab7dc6aad</id>
<content type='text'>
added a sysfs interface for thermal throttling, then userspace
can get/update thermal limit

Signed-off-by: Kun Liu &lt;Kun.Liu2@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: implement mode2 reset on smu_v13_0_10</title>
<updated>2023-02-14T20:47:15+00:00</updated>
<author>
<name>Kenneth Feng</name>
<email>kenneth.feng@amd.com</email>
</author>
<published>2023-02-10T05:04:17+00:00</published>
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<id>urn:sha1:230dd6bb61173acccdfbf855ba907286e850cd67</id>
<content type='text'>
implement mode2 reset on smu_v13_0_10

Signed-off-by: Kenneth Feng &lt;kenneth.feng@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Add detailed GFXOFF stats to debugfs</title>
<updated>2022-08-16T22:17:31+00:00</updated>
<author>
<name>André Almeida</name>
<email>andrealmeid@igalia.com</email>
</author>
<published>2022-08-10T23:28:55+00:00</published>
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<id>urn:sha1:0ad7347a64ac4baec1786810709eebedc5f823d5</id>
<content type='text'>
Add debugfs interface to log GFXOFF statistics:

- Read amdgpu_gfxoff_count to get the total GFXOFF entry count at the
  time of query since system power-up

- Write 1 to amdgpu_gfxoff_residency to start logging, and 0 to stop.
  Read it to get average GFXOFF residency % multiplied by 100
  during the last logging interval.

Both features are designed to be keep the values persistent between
suspends.

Signed-off-by: André Almeida &lt;andrealmeid@igalia.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: introduce runtime pm mode</title>
<updated>2022-07-18T20:42:39+00:00</updated>
<author>
<name>Guchun Chen</name>
<email>guchun.chen@amd.com</email>
</author>
<published>2022-07-14T07:32:51+00:00</published>
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<id>urn:sha1:50fe04d46aab77cf8fc3d48fbc38d872d181a849</id>
<content type='text'>
It can benefit code consistency in future.

Suggested-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Guchun Chen &lt;guchun.chen@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/pm: implement the SMU_MSG_EnableGfxImu function</title>
<updated>2022-06-03T20:44:15+00:00</updated>
<author>
<name>Huang Rui</name>
<email>ray.huang@amd.com</email>
</author>
<published>2022-05-18T13:19:32+00:00</published>
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<id>urn:sha1:7101ab97e3b00ec1c68d09826bb0521d17783673</id>
<content type='text'>
GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU.

Signed-off-by: Huang Rui &lt;ray.huang@amd.com&gt;
Reviewed-by: Tim Huang &lt;Tim.Huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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