kernel/linux.git/drivers/gpu/drm/amd/pm/amdgpu_pm.c, branch v5.19Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v5.192022-05-16T18:20:55+00:00drm/amd/pm: consistent approach for smartshift2022-05-16T18:20:55+00:00Sathishkumar Ssathishkumar.sundararaju@amd.com2022-05-11T11:48:31+00:00urn:sha1:494c1432542b33f8577bd59e5b084fd50bade6d0
create smartshift sysfs attributes from dGPU device even
on smartshift 1.0 platform to be consistent. Do not populate
the attributes on platforms that have APU only but not dGPU
or vice versa.
V2:
avoid checking for the number of VGA/DISPLAY devices (Lijo)
move code to read from dGPU or APU into a function and reuse (Lijo)
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu/pm: Disallow managing power profiles on SRIOV for Sienna Cichlid2022-05-10T21:53:13+00:00Danijel Slivkadanijel.slivka@amd.com2022-05-05T14:45:32+00:00urn:sha1:1b85257290f382a78adba1b0a5b59a95cebdfa2f
Managing power profiles mode is not allowed in SRIOV mode for Sienna
Cichlid. This patch is adjusting the "pp_power_profile_mode" and
"power_dpm_force_performance_level" accordingly.
Signed-off-by: Danijel Slivka <danijel.slivka@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/pm: enable workload type change on smu_v13_0_72022-05-06T14:36:12+00:00Kenneth Fengkenneth.feng@amd.com2022-04-22T03:40:51+00:00urn:sha1:334682ae81513638aa49da9615c2c0054a711ed4
enable workload type change on smu_v13_0_7
v2: squash in out of bounds fix (Alex)
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/pm: enable pp_dpm_vclk/dclk interface for smu_v13_0_72022-05-05T20:53:37+00:00Kenneth Fengkenneth.feng@amd.com2022-04-12T09:07:24+00:00urn:sha1:3929f3381e9cc61f73070377825b62667243bfb4
enable pp_dpm_vclk/dclk interface for smu_v13_0_7
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable more GFX clockgating features for GC 11.0.02022-05-05T20:50:58+00:00Evan Quanevan.quan@amd.com2022-04-11T06:39:59+00:00urn:sha1:915b5ce774b5d59f90f970f97a7295f12cf898bc
Support more GFX clockgating features(3D_CGCG, 3D_CGLS, MGCG,
FGCG and PERF_CLK).
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add FGCG support2022-05-04T14:02:56+00:00Evan Quanevan.quan@amd.com2022-04-07T13:51:41+00:00urn:sha1:d6b9a91f5d1bd9f8027dbab1119a3a51f0afed26
Add the CG flag for Fine Grained Clock Gating.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/smu: Update SMU13 support for SMU 13.0.02022-05-04T13:58:46+00:00Evan Quanevan.quan@amd.com2022-04-06T21:13:54+00:00urn:sha1:276c03a0547068026241decd2c1159df0be5941f
Modify the common smu13 code and add a new smu
13.0.0 ppt file to handle the smu 13.0.0 specific
configuration.
v2: squash in typo fix in profile name
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/pm: enable pp_dpm_vclk/dclk sysfs interface support for SMU 13.0.02022-05-04T13:57:39+00:00Evan Quanevan.quan@amd.com2022-03-18T06:35:05+00:00urn:sha1:64440743e89629231fee712879d7a9d5ec7dfb8c
Make the pp_dpm_vclk/dclk sysfs interfaces visible for SMU 13.0.0.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: expand cg_flags from u32 to u642022-04-08T21:24:24+00:00Evan Quanevan.quan@amd.com2022-03-25T10:00:02+00:00urn:sha1:25faeddcf3c3f31f9f43de5c55f7cbdd13d3ebc7
With this, we can support more CG flags.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
amdgpu/pm: Enable sysfs nodes for vclk and dclk for NAVI122022-04-05T14:26:28+00:00Marko ZekovicMarko.Zekovic@amd.com2022-03-28T10:37:30+00:00urn:sha1:a68bec2ce7d6d89136b91160c3428caf683acb91
SMI clock measure API is failing on NAVI12, because
sysfs node for pp_dpm_vclk is not existing. Enable
sysfs node for pp_dpm_vclk for NAVI12.
v2: Also enable sysfs node for pp_dpm_dclk.
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Marko Zekovic <Marko.Zekovic@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>