kernel/linux.git/drivers/gpu/drm/amd/include, branch v6.9.12

drm/amdgpu/pptable: Fix UBSAN array-index-out-of-bounds

2024-07-25T07:53:24+00:00

[ Upstream commit c6c4dd54012551cce5cde408b35468f2c62b0cce ] Flexible arrays used [1] instead of []. Replace the former with the latter to resolve multiple UBSAN warnings observed on boot with a BONAIRE card. In addition, use the __counted_by attribute where possible to hint the length of the arrays to the compiler and any sanitizers. Signed-off-by: Tasos Sahanidis Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amdgpu: silence UBSAN warning

2024-07-11T10:51:23+00:00

[ Upstream commit 05d9e24ddb15160164ba6e917a88c00907dc2434 ] Convert a variable sized array from [1] to []. Reviewed-by: Christian König Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amdgpu/atomfirmware: silence UBSAN warning

2024-07-11T10:51:17+00:00

commit d0417264437a8fa05f894cabba5a26715b32d78e upstream. This is a variable sized array. Link: https://lists.freedesktop.org/archives/amd-gfx/2024-June/110420.html Tested-by: Jeff Layton Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman

drm/amdgpu/atomfirmware: add intergrated info v2.3 table

2024-06-16T11:51:01+00:00

commit e64e8f7c178e5228e0b2dbb504b9dc75953a319f upstream. [Why] The vram width value is 0. Because the integratedsysteminfo table in VBIOS has updated to 2.3. [How] Driver needs a new intergrated info v2.3 table too. Then the vram width value will be correct. Signed-off-by: Li Ma Reviewed-by: Yifan Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman

drm/amdgpu/umsch: update UMSCH 4.0 FW interface

2024-03-27T13:29:42+00:00

Align with FW changes. Signed-off-by: Lang Yu Reviewed-by: Veerabadhran Gopalakrishnan Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: Add pcie v6_1_0 ip headers (v5)

2024-03-07T20:32:38+00:00

v1: Add pcie v6_1_0 register offset and shift masks header files. (Hawking) v2: Update pcie v6_1_0 register offset and shift masks header files to RE2. (Likun) v3: Update pcie v6_1_0 register offset and shift masks header files to RE2.5. (Likun) v4: Update pcie v6_1_0 register offset and shift masks header files to RE3. (Likun) v5: Updates (Alex) Signed-off-by: Hawking Zhang Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher

drm/amdgpu: Add nbif v6_3_1 ip headers (v5)

2024-03-07T20:32:31+00:00

v1: Add nbif v6_3_1 register offset and shift masks header files. (Hawking) v2: Update nbif v6_3_1 register offset and shift masks header files to RE2. (Likun) v3: Update nbif v6_3_1 register offset and shift masks header files to RE2.5. (Likun) v4: Update nbif v6_3_1 register offset and shift masks header files to RE3. (Likun) v5: Updates (Alex) Signed-off-by: Hawking Zhang Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang Reviewed-by: Likun Gao Signed-off-by: Alex Deucher

drm/amd: add register headers for DCN351

2024-03-04T20:59:07+00:00

Add register headers for DCN 3.5.1. Signed-off-by: Hamza Mahfooz Signed-off-by: Alex Deucher

drm/amd: Update atomfirmware.h for DCN401

2024-02-22T15:26:32+00:00

Add new firmware header definitions reqiured for DCN401 Signed-off-by: Aurabindo Pillai Acked-by: Alex Deucher Signed-off-by: Alex Deucher

Revert "drm/amdgpu: Add pci usage to nbio v7.9"

2024-02-22T15:15:26+00:00

Remove implementation to get pcie usage for nbio v7.9 as pcie usage is handled by fw This reverts commit 59070fd9ccea58c3363d39f69c25fa98c71eb02f. Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher