<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/include, branch v6.6.18</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.18</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.18'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2024-02-05T20:14:30+00:00</updated>
<entry>
<title>Re-revert "drm/amd/display: Enable Replay for static screen use cases"</title>
<updated>2024-02-05T20:14:30+00:00</updated>
<author>
<name>Ivan Lipski</name>
<email>ivlipski@amd.com</email>
</author>
<published>2023-10-02T17:47:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=90df72694a5b7ca2a415eb3baeb9f385cee8033c'/>
<id>urn:sha1:90df72694a5b7ca2a415eb3baeb9f385cee8033c</id>
<content type='text'>
[ Upstream commit d6398866a6b47e92319ef6efdb0126a4fbb7796a ]

This reverts commit 44e60b14d5a72f91fd0bdeae8da59ae37a3ca8e5.

Since, it causes a regression in which eDP displays with PSR support,
but no Replay support (Sink support &lt;= 0x03), fail to enable PSR and
consequently all IGT amd_psr tests fail. So, revert this until a more
suitable fix can be found.

This got brought back accidently with the backmerge.

Acked-by: Leo Li &lt;sunpeng.li@amd.com&gt;
Signed-off-by: Ivan Lipski &lt;ivlipski@amd.com&gt;
Signed-off-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: fix mes set shader debugger process management</title>
<updated>2024-02-05T20:14:28+00:00</updated>
<author>
<name>Jonathan Kim</name>
<email>jonathan.kim@amd.com</email>
</author>
<published>2023-12-05T17:22:07+00:00</published>
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<id>urn:sha1:3a950c56dea199d65bc98db348c017856aa2f194</id>
<content type='text'>
[ Upstream commit bd33bb1409b494558a2935f7bbc7842def957fcd ]

MES provides the driver a call to explicitly flush stale process memory
within the MES to avoid a race condition that results in a fatal
memory violation.

When SET_SHADER_DEBUGGER is called, the driver passes a memory address
that represents a process context address MES uses to keep track of
future per-process calls.

Normally, MES will purge its process context list when the last queue
has been removed.  The driver, however, can call SET_SHADER_DEBUGGER
regardless of whether a queue has been added or not.

If SET_SHADER_DEBUGGER has been called with no queues as the last call
prior to process termination, the passed process context address will
still reside within MES.

On a new process call to SET_SHADER_DEBUGGER, the driver may end up
passing an identical process context address value (based on per-process
gpu memory address) to MES but is now pointing to a new allocated buffer
object during KFD process creation.  Since the MES is unaware of this,
access of the passed address points to the stale object within MES and
triggers a fatal memory violation.

The solution is for KFD to explicitly flush the process context address
from MES on process termination.

Note that the flush call and the MES debugger calls use the same MES
interface but are separated as KFD calls to avoid conflicting with each
other.

Signed-off-by: Jonathan Kim &lt;jonathan.kim@amd.com&gt;
Tested-by: Alice Wong &lt;shiwei.wong@amd.com&gt;
Reviewed-by: Eric Huang &lt;jinhuieric.huang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Force order between a read and write to the same address</title>
<updated>2023-12-08T07:52:17+00:00</updated>
<author>
<name>Alex Sierra</name>
<email>alex.sierra@amd.com</email>
</author>
<published>2023-11-20T17:31:32+00:00</published>
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<id>urn:sha1:5ffd8c73d1d0f38706951c4ab8710cb6c6cdde45</id>
<content type='text'>
commit 4b27a33c3b173bef1d19ba89e0b9b812b4fddd25 upstream.

Setting register to force ordering to prevent read/write or write/read
hazards for un-cached modes.

Signed-off-by: Alex Sierra &lt;alex.sierra@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amd: Fix UBSAN array-index-out-of-bounds for SMU7</title>
<updated>2023-11-28T17:19:40+00:00</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-10-04T20:22:52+00:00</published>
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<id>urn:sha1:92a775e7c9707aed28782bafe636bf87675f5a97</id>
<content type='text'>
[ Upstream commit 760efbca74a405dc439a013a5efaa9fadc95a8c3 ]

For pptable structs that use flexible array sizes, use flexible arrays.

Suggested-by: Felix Held &lt;felix.held@amd.com&gt;
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2874
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Store CU info from all XCCs for GFX v9.4.3</title>
<updated>2023-09-11T22:16:31+00:00</updated>
<author>
<name>Mukul Joshi</name>
<email>mukul.joshi@amd.com</email>
</author>
<published>2023-08-25T15:59:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=97e3c6a853f2af9145daf0c6ca25bcdf55c759d4'/>
<id>urn:sha1:97e3c6a853f2af9145daf0c6ca25bcdf55c759d4</id>
<content type='text'>
Currently, we store CU info only for a single XCC assuming
that it is the same for all XCCs. However, that may not be
true. As a result, store CU info for all XCCs. This info is
later used for CU masking.

Signed-off-by: Mukul Joshi &lt;mukul.joshi@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Fix reg offset for setting CWSR grace period</title>
<updated>2023-09-11T22:15:43+00:00</updated>
<author>
<name>Mukul Joshi</name>
<email>mukul.joshi@amd.com</email>
</author>
<published>2023-08-28T18:18:23+00:00</published>
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<id>urn:sha1:81faf9e0c3d39d47c6825469591d60a2cd0bbe10</id>
<content type='text'>
This patch fixes the case where the code currently passes
absolute register address and not the reg offset, which HWS
expects, when sending the PM4 packet to set/update CWSR grace
period. Additionally, cleanup the signature of
build_grace_period_packet_info function as it no longer needs
the inst parameter.

Signed-off-by: Mukul Joshi &lt;mukul.joshi@amd.com&gt;
Reviewed-by: Jonathan Kim &lt;jonathan.kim@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add umc_info v4_0 structure</title>
<updated>2023-08-31T22:09:38+00:00</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2023-08-23T09:41:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=48d02dcba17aae6a1de4f9814aa5cbe4c977abbb'/>
<id>urn:sha1:48d02dcba17aae6a1de4f9814aa5cbe4c977abbb</id>
<content type='text'>
To be used by aqua_vanjaram

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Candice Li &lt;candice.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update gc_info v2_1 from discovery</title>
<updated>2023-08-31T21:53:19+00:00</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2023-08-14T10:37:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=46b55e25c94af1689636f4be1760fb0d9ddd8ae2'/>
<id>urn:sha1:46b55e25c94af1689636f4be1760fb0d9ddd8ae2</id>
<content type='text'>
Several new fields are exposed in gc_info v2_1

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Shiwu Zhang &lt;shiwu.zhang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update mall info v2 from discovery</title>
<updated>2023-08-31T21:53:08+00:00</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2023-08-14T08:27:59+00:00</published>
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<id>urn:sha1:d4f6425a5615bbeaee1d14663205b23f82dc0313</id>
<content type='text'>
Mall info v2 is introduced in ip discovery

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Shiwu Zhang &lt;shiwu.zhang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable Replay for static screen use cases</title>
<updated>2023-08-31T21:51:50+00:00</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>Bhawanpreet.Lakha@amd.com</email>
</author>
<published>2023-05-16T16:21:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=44e60b14d5a72f91fd0bdeae8da59ae37a3ca8e5'/>
<id>urn:sha1:44e60b14d5a72f91fd0bdeae8da59ae37a3ca8e5</id>
<content type='text'>
- Setup replay config on device init.
- Enable replay if feature is enabled (prioritize replay over PSR, since
it can be enabled in more usecases)
- Add debug masks to enable replay on supported ASICs

Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
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