<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/include, branch v6.6.12</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.12</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.12'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2023-12-08T07:52:17+00:00</updated>
<entry>
<title>drm/amdgpu: Force order between a read and write to the same address</title>
<updated>2023-12-08T07:52:17+00:00</updated>
<author>
<name>Alex Sierra</name>
<email>alex.sierra@amd.com</email>
</author>
<published>2023-11-20T17:31:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=5ffd8c73d1d0f38706951c4ab8710cb6c6cdde45'/>
<id>urn:sha1:5ffd8c73d1d0f38706951c4ab8710cb6c6cdde45</id>
<content type='text'>
commit 4b27a33c3b173bef1d19ba89e0b9b812b4fddd25 upstream.

Setting register to force ordering to prevent read/write or write/read
hazards for un-cached modes.

Signed-off-by: Alex Sierra &lt;alex.sierra@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.1.x
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>drm/amd: Fix UBSAN array-index-out-of-bounds for SMU7</title>
<updated>2023-11-28T17:19:40+00:00</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-10-04T20:22:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=92a775e7c9707aed28782bafe636bf87675f5a97'/>
<id>urn:sha1:92a775e7c9707aed28782bafe636bf87675f5a97</id>
<content type='text'>
[ Upstream commit 760efbca74a405dc439a013a5efaa9fadc95a8c3 ]

For pptable structs that use flexible array sizes, use flexible arrays.

Suggested-by: Felix Held &lt;felix.held@amd.com&gt;
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2874
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Store CU info from all XCCs for GFX v9.4.3</title>
<updated>2023-09-11T22:16:31+00:00</updated>
<author>
<name>Mukul Joshi</name>
<email>mukul.joshi@amd.com</email>
</author>
<published>2023-08-25T15:59:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=97e3c6a853f2af9145daf0c6ca25bcdf55c759d4'/>
<id>urn:sha1:97e3c6a853f2af9145daf0c6ca25bcdf55c759d4</id>
<content type='text'>
Currently, we store CU info only for a single XCC assuming
that it is the same for all XCCs. However, that may not be
true. As a result, store CU info for all XCCs. This info is
later used for CU masking.

Signed-off-by: Mukul Joshi &lt;mukul.joshi@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Fix reg offset for setting CWSR grace period</title>
<updated>2023-09-11T22:15:43+00:00</updated>
<author>
<name>Mukul Joshi</name>
<email>mukul.joshi@amd.com</email>
</author>
<published>2023-08-28T18:18:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=81faf9e0c3d39d47c6825469591d60a2cd0bbe10'/>
<id>urn:sha1:81faf9e0c3d39d47c6825469591d60a2cd0bbe10</id>
<content type='text'>
This patch fixes the case where the code currently passes
absolute register address and not the reg offset, which HWS
expects, when sending the PM4 packet to set/update CWSR grace
period. Additionally, cleanup the signature of
build_grace_period_packet_info function as it no longer needs
the inst parameter.

Signed-off-by: Mukul Joshi &lt;mukul.joshi@amd.com&gt;
Reviewed-by: Jonathan Kim &lt;jonathan.kim@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add umc_info v4_0 structure</title>
<updated>2023-08-31T22:09:38+00:00</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2023-08-23T09:41:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=48d02dcba17aae6a1de4f9814aa5cbe4c977abbb'/>
<id>urn:sha1:48d02dcba17aae6a1de4f9814aa5cbe4c977abbb</id>
<content type='text'>
To be used by aqua_vanjaram

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Candice Li &lt;candice.li@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update gc_info v2_1 from discovery</title>
<updated>2023-08-31T21:53:19+00:00</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2023-08-14T10:37:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=46b55e25c94af1689636f4be1760fb0d9ddd8ae2'/>
<id>urn:sha1:46b55e25c94af1689636f4be1760fb0d9ddd8ae2</id>
<content type='text'>
Several new fields are exposed in gc_info v2_1

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Shiwu Zhang &lt;shiwu.zhang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update mall info v2 from discovery</title>
<updated>2023-08-31T21:53:08+00:00</updated>
<author>
<name>Le Ma</name>
<email>le.ma@amd.com</email>
</author>
<published>2023-08-14T08:27:59+00:00</published>
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<id>urn:sha1:d4f6425a5615bbeaee1d14663205b23f82dc0313</id>
<content type='text'>
Mall info v2 is introduced in ip discovery

Signed-off-by: Le Ma &lt;le.ma@amd.com&gt;
Reviewed-by: Shiwu Zhang &lt;shiwu.zhang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Lijo Lazar &lt;lijo.lazar@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable Replay for static screen use cases</title>
<updated>2023-08-31T21:51:50+00:00</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>Bhawanpreet.Lakha@amd.com</email>
</author>
<published>2023-05-16T16:21:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=44e60b14d5a72f91fd0bdeae8da59ae37a3ca8e5'/>
<id>urn:sha1:44e60b14d5a72f91fd0bdeae8da59ae37a3ca8e5</id>
<content type='text'>
- Setup replay config on device init.
- Enable replay if feature is enabled (prioritize replay over PSR, since
it can be enabled in more usecases)
- Add debug masks to enable replay on supported ASICs

Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Rename AMDGPU_PP_SENSOR_GPU_POWER</title>
<updated>2023-08-15T22:08:30+00:00</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-08-10T10:32:01+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9366c2e87d08b88332a363adc537962ba3840fd9'/>
<id>urn:sha1:9366c2e87d08b88332a363adc537962ba3840fd9</id>
<content type='text'>
Use the clearer name `AMDGPU_PP_SENSOR_GPU_AVG_POWER` instead.

Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER`</title>
<updated>2023-08-15T22:08:29+00:00</updated>
<author>
<name>Mario Limonciello</name>
<email>mario.limonciello@amd.com</email>
</author>
<published>2023-08-10T10:31:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=47f1724db4fe0085b33cafd68bb8b7267678bb95'/>
<id>urn:sha1:47f1724db4fe0085b33cafd68bb8b7267678bb95</id>
<content type='text'>
Some GPUs have been overloading average power values and input power
values. To disambiguate these, introduce a new
`AMDGPU_PP_SENSOR_GPU_INPUT_POWER` and the GPUs that share input
power update to use this instead of average power.

Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2746
Signed-off-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
