kernel/linux.git/drivers/gpu/drm/amd/include, branch v6.19.11

drm/amdgpu: Describe @AMD_IP_BLOCK_TYPE_RAS in amd_ip_block_type enum

2026-02-26T23:00:58+00:00

[ Upstream commit d8ccbb5e228b093eba19027a281274e7faf2da4c ] Sphinx reports kernel-doc warning: WARNING: ./drivers/gpu/drm/amd/include/amd_shared.h:113 Enum value 'AMD_IP_BLOCK_TYPE_RAS' not described in enum 'amd_ip_block_type' Describe the value to fix it. Fixes: 7169e706c82d ("drm/amdgpu: Add ras module ip block to amdgpu discovery") Signed-off-by: Bagas Sanjaya Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amdgpu/vce1: Clean up register definitions

2025-11-12T02:54:18+00:00

The sid.h header contained some VCE1 register definitions, but they were using byte offsets (probably copied from the old radeon driver). Move all of these to the proper VCE1 headers and ensure they are in dword offsets. Also add the register definitions that we need for the firmware validation mechanism in VCE1. Signed-off-by: Timur Kristóf Co-developed-by: Alexandre Demers Signed-off-by: Alexandre Demers Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amd/pm: Add schema v1.1 for parition metrics

2025-11-04T16:53:21+00:00

Use a schema similar to gpu metrics v1.9 for partition metrics also. It will have field type encoded followed by the field value(s). The attribute ids used will be shared with gpu metrics. The structure definition is only to distinguish between gpu metrics and partition metrics though both gpu metrics v1.9 and partition metrics v1.1 follow the same definition. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal Signed-off-by: Alex Deucher

drm/amdgpu/pm: Add definition for gpu_metrics v1.9

2025-10-28T14:10:32+00:00

Add gpu metrics definition which is only a set of gpu metrics attributes. A field is encoded by its id, type and number of instances. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal Signed-off-by: Alex Deucher

drm/amdgpu: fix SPDX header on irqsrcs_vcn_5_0.h

2025-10-28T13:52:36+00:00

This should be MIT. The driver in general is MIT and the license text at the top of the file is MIT so fix it. Fixes: d1bb64651095 ("drm/amdgpu: add irq source ids for VCN5_0/JPEG5_0") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4654 Reviewed-by: Mario Limonciello Signed-off-by: Alex Deucher

drm/amdgpu: fix SPDX header on amd_cper.h

2025-10-28T13:52:22+00:00

This should be MIT. The driver in general is MIT and the license text at the top of the file is MIT so fix it. Fixes: 523b69c65445 ("drm/amd/include: Add amd cper header") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4654 Reviewed-by: Mario Limonciello Signed-off-by: Alex Deucher

drm/amdgpu: Add ras module ip block to amdgpu discovery

2025-10-20T22:25:54+00:00

Add ras module ip block to amdgpu discovery. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: update remove after reset flag for MES remove queue

2025-10-13T18:14:36+00:00

Remove queue after reset flag is required to remove a queue that has been successfully reset to clean up the MES' internal state. Signed-off-by: Jonathan Kim Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd: Stop overloading power limit with limit type

2025-10-13T18:14:35+00:00

When passed around internally the upper 8 bits of power limit include the limit type. This is non-obvious without digging into the nuances of each function. Instead pass the limit type as an argument to all applicable layers. Reviewed-by: Lijo Lazar Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher

drm/amdgpu: Add additional DCE6 SCL registers

2025-10-07T18:09:06+00:00

Fixes: 102b2f587ac8 ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)") Signed-off-by: Alex Deucher