kernel/linux.git/drivers/gpu/drm/amd/include, branch v6.12.80Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.802026-03-25T10:08:46+00:00drm/amd/display: Add pixel_clock to amd_pp_display_configuration2026-03-25T10:08:46+00:00Timur Kristóftimur.kristof@gmail.com2025-09-09T14:17:50+00:00urn:sha1:c179bece52fd29ebd4e6a52f1695c03879dd2034
commit b515dcb0dc4e85d8254f5459cfb32fce88dacbfb upstream.
This commit adds the pixel_clock field to the display config
struct so that power management (DPM) can use it.
We currently don't have a proper bandwidth calculation on old
GPUs with DCE 6-10 because dce_calcs only supports DCE 11+.
So the power management (DPM) on these GPUs may need to make
ad-hoc decisions for display based on the pixel clock.
Also rename sym_clock to pixel_clock in dm_pp_single_disp_config
to avoid confusion with other code where the sym_clock refers to
the DisplayPort symbol clock.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amdgpu: Add additional DCE6 SCL registers2025-10-19T14:33:42+00:00Alex Deucheralexander.deucher@amd.com2025-09-25T18:45:21+00:00urn:sha1:9626d3af3cd1fe79401ceb82039ed10450867a55
[ Upstream commit 507296328b36ffd00ec1f4fde5b8acafb7222ec7 ]
Fixes: 102b2f587ac8 ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drm/amdgpu: Enable MES lr_compute_wa by default2025-10-12T10:57:17+00:00Mario Limonciellomario.limonciello@amd.com2025-09-19T00:48:00+00:00urn:sha1:5980a35c9d138804251e50788c1e8137028a47ac
commit 1fb710793ce2619223adffaf981b1ff13cd48f17 upstream.
The MES set resources packet has an optional bit 'lr_compute_wa'
which can be used for preventing MES hangs on long compute jobs.
Set this bit by default.
Co-developed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amd/include : Update MES v12 API for fence update2025-10-12T10:57:17+00:00Shaoyun Liushaoyun.liu@amd.com2025-02-05T17:33:11+00:00urn:sha1:2dedc6b77bf82dae6cf6a9d4d5ac44526be9a605
commit 15d8c92f107c17c2e585cb4888c67873538f9722 upstream.
MES fence_value will be updated in fence_addr if API success,
otherwise upper 32 bit will be used to indicate error code.
In any case, MES will trigger an EOP interrupt with 0xb1 as
context id in the interrupt cookie
Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amd/include : MES v11 and v12 API header update2025-10-12T10:57:17+00:00Shaoyun Liushaoyun.liu@amd.com2025-02-05T18:16:45+00:00urn:sha1:ff2b82286fc8e6fc6caf9072009d78f7c05db32e
commit 1c687c0da9efb7c627793483a8927554764e7a55 upstream.
MES requires driver set cleaner_shader_fence_mc_addr
for cleaner shader support.
Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amd : Update MES API header file for v11 & v122025-10-12T10:57:17+00:00Shaoyun Liushaoyun.liu@amd.com2024-10-18T19:56:25+00:00urn:sha1:bfd0bec4cb2c0b9e30decc84ffc269ba91ee6906
commit ce4971388c79d36b3f50f607c3278dbfae6c789b upstream.
New features require the new fields defines
Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amdgpu: Set snoop bit for SDMA for MI series2025-05-29T09:02:52+00:00Harish KasiviswanathanHarish.Kasiviswanathan@amd.com2025-02-04T22:57:47+00:00urn:sha1:452807a863018375186790bed955382b6bd5829e
[ Upstream commit 3394b1f76d3f8adf695ceed350a5dae49003eb37 ]
SDMA writes has to probe invalidate RW lines. Set snoop bit in mmhub for
this to happen.
v2: Missed a few mmhub_v9_4. Added now.
v3: Calculate hub offset once since it doesn't change inside the loop
Modified function names based on review comments.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drm/amd: Add some missing straps from NBIO 7.11.02024-12-09T09:41:14+00:00Mario Limonciellomario.limonciello@amd.com2024-11-18T17:46:10+00:00urn:sha1:be51376b1f500f455d7403590b5e617f2f1444cd
commit 902fbbf429b8213232b18de0ddfd5c0f3851cb8f upstream.
Earlier ASICs have strap information exported, and this is missing
for NBIO 7.11.0.
Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Fixes: ca8c68142ad8 ("drm/amdgpu: add nbio 7.11 registers")
Link: https://lore.kernel.org/r/20241118174611.10700-1-mario.limonciello@amd.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amdkfd: Update logic for CU occupancy calculations2024-09-25T16:56:00+00:00Mukul Joshimukul.joshi@amd.com2024-09-16T18:33:58+00:00urn:sha1:6ae9e1aba97e4cdaa31a0bfdc07497ad0e915c84
Currently, the code uses the IH_VMID_X_LUT register to map
a queue's vmid to the corresponding PASID. This logic is racy
since CP can update the VMID-PASID mapping anytime especially
when there are more processes than number of vmids. Update the
logic to calculate CU occupancy by matching doorbell offset of
the queue with valid wave counts against the process's queues.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: fix spelling in amd_shared.h2024-09-18T20:14:26+00:00Alex Deucheralexander.deucher@amd.com2024-09-10T14:19:43+00:00urn:sha1:902b4027216aeaabe1562e1db070550c06f3ec89
Fix spelling in documentation.
Reviewed-by: Kent Russell <kent.russell@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>