kernel/linux.git/drivers/gpu/drm/amd/include, branch v6.11.8Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.11.82024-09-10T21:27:17+00:00drm/amdgpu/atomfirmware: Silence UBSAN warning2024-09-10T21:27:17+00:00Alex Deucheralexander.deucher@amd.com2024-09-06T14:42:45+00:00urn:sha1:17ea4383649fdeaff3181ddcf1ff03350d42e591
Per the comments, these are variable sized arrays.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3613
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 81f7804ba84ee617ed594de934ed87bcc4f83531)
Cc: stable@vger.kernel.org
drm/amdgpu: support for gc_info table v1.32024-08-28T14:05:54+00:00Likun GaoLikun.Gao@amd.com2024-08-22T03:44:12+00:00urn:sha1:6d5064c379557d92832b51d247b385bb8bd6aa5b
Add gc_info table v1.3 for IP discovery.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 875ff9a7ee8824200885384effa7743892a34ed6)
drm/amdgpu/mes12: update mes_v12_api_def.h2024-08-13T17:04:40+00:00Jack XiaoJack.Xiao@amd.com2024-08-07T03:43:45+00:00urn:sha1:278e1865b7a2124ea783b75ea8b3ee0bc2da5d85
Update mes12 api definition.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 2ab5dc59177419d8a49e89585e82ff41524270fc)
drm/amdgpu: increase mes log buffer size for gfx122024-07-27T22:10:12+00:00Michael Chenmichael.chen@amd.com2024-07-23T21:45:23+00:00urn:sha1:9038e25c80558d48ce33d6d8c168666164dc72e9
MES firmware requires larger log buffer for gfx12. Allocate
proper buffer respectively for gfx11 and gfx12.
Signed-off-by: Michael Chen <michael.chen@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 739d0f3e1f36738d4cd84166784a8f7a58d69612)
drm/amdgpu: Fix atomics on GFX122024-07-24T21:30:23+00:00David Belangerdavid.belanger@amd.com2024-06-10T20:38:55+00:00urn:sha1:73048bda46c3085df5fd42840de09523386d3e54
If PCIe supports atomics, configure register to prevent DF from
breaking atomics in separate load/store operations.
Signed-off-by: David Belanger <david.belanger@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 666f14cab21b17ccc1bdfe1e82458aa429b3b7e0)
drm/amdgpu/atomfirmware: silence UBSAN warning2024-07-02T22:07:31+00:00Alex Deucheralexander.deucher@amd.com2024-07-01T16:50:10+00:00urn:sha1:4ed6a3689caba239e6df18c60af9489001f481c3
This is a variable sized array.
Link: https://lists.freedesktop.org/archives/amd-gfx/2024-June/110420.html
Tested-by: Jeff Layton <jlayton@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Map ISP interrupts as generic IRQs2024-06-27T21:34:40+00:00Pratap Nirujogipratap.nirujogi@amd.com2024-05-08T02:49:46+00:00urn:sha1:0253d718a070ba109046299847fe8f3cf7568c3c
Map ISP IH interrupts to Linux generic IRQ for ISP driver to
handle the interrupts using MFD IORESOURCE_IRQ resource.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add ISP support to amdgpu_discovery2024-06-27T21:34:39+00:00Pratap Nirujogipratap.nirujogi@amd.com2024-05-02T20:51:39+00:00urn:sha1:772e4d56dab5448eb120f74811eaa71d7a474c1f
ISP hw block is supported in some of the AMD GPU versions, add support
to discover ISP IP in amdgpu_discovery.
v2: squash in documentation update (Alex)
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add some missing register definitions2024-06-27T21:32:17+00:00Aurabindo Pillaiaurabindo.pillai@amd.com2024-06-25T18:17:46+00:00urn:sha1:ad89e904e3aaa93628785546034ec77f3100cf79
Add some register offsets that are required for Display DCC on DCN401
Fixes: 2d072b445622 ("drm/amd: Add reg definitions for DCN401 DCC")
Reported-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add reg definitions for DCN401 DCC2024-06-27T21:10:38+00:00Aurabindo Pillaiaurabindo.pillai@amd.com2024-06-14T19:42:55+00:00urn:sha1:2d072b445622b90f8a961c0376887120da75221f
[WHAT]
Add the necessary register definitions to enable DCC on DCN4x
Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>