kernel/linux.git/drivers/gpu/drm/amd/include, branch v5.4.227

drm/amdgpu: Update NV SIMD-per-CU to 2

2021-07-19T06:53:14+00:00

commit aa6158112645aae514982ad8d56df64428fcf203 upstream. Navi series GPUs have 2 SIMDs per CU (and then 2 CUs per WGP). The NV enum headers incorrectly listed this as 4, which later meant we were incorrectly reporting the number of SIMDs in the HSA topology. This could cause problems down the line for user-space applications that want to launch a fixed amount of work to each SIMD. Signed-off-by: Joseph Greathouse Reviewed-by: Alex Deucher Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman

amdgpu/gmc_v9: save/restore sdpif regs during S3

2020-03-05T15:43:43+00:00

commit a3ed353cf8015ba84a0407a5dc3ffee038166ab0 upstream. fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM. Suggested-by: Alex Deucher Signed-off-by: Shirish S Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman

drm/amdgpu/discovery: reserve discovery data at the top of VRAM

2020-01-17T18:48:51+00:00

commit 5f6a556f98de425fcb7928456839a06f02156633 upstream. IP Discovery data is TMR fenced by the latest PSP BL, so we need to reserve this region. Tested on navi10/12/14 with VBIOS integrated with latest PSP BL. v2: use DISCOVERY_TMR_SIZE macro as bo size use amdgpu_bo_create_kernel_at() to allocate bo Signed-off-by: Xiaojie Yuan Reviewed-by: Hawking Zhang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman

drm/amd/display: update renoir_ip_offset.h

2019-09-17T19:22:29+00:00

This patch updates MP1_BASE in renoir_ip_offset.h Signed-off-by: Aaron Liu Acked-by: Roman Li Signed-off-by: Alex Deucher

drm/amdgpu: update IH_CHICKEN in oss 4.0 IP header for VG/RV series

2019-08-30T20:37:17+00:00

In Renoir's emulator, those chicken bits need to be programmed. Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Reviewed-by: Hawking Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd/display: Add Renoir registers (v3)

2019-08-29T20:52:32+00:00

add registers for dcn, clk, and renoir ip offsets v2: header cleanup (Alex) v3: Add DPCS registers (Hersen) Acked-by: Harry Wentland Signed-off-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/powerplay: Add interface to lock SMU HW I2C.

2019-08-27T13:17:42+00:00

v2: PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict over I2C bus and engine disable thermal control access to force SMU stop using the I2C bus until the issue is reslolved. Expose and call vega20_is_smc_ram_running to skip locking when SMU FW is not yet loaded. v3: Remove the prevoius hack as the SMU found the bug. v5: Typo fix Signed-off-by: Andrey Grodzovsky Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amd: Import smuio_11_0 headers for EEPROM access on Vega20

2019-08-27T13:17:27+00:00

v3: Merge CKSVII2C_IC regs into exsisting headers. Signed-off-by: Andrey Grodzovsky Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu/display: add flag for multi-display mclk switching

2019-08-23T16:33:00+00:00

Add a dcfeaturemask flag for mclk switching. Disable by default; enable once the feature has seen more testing. Set amdgpu.dcfeaturemask=2 on the kernel command line in grub to enable this. Acked-by: Evan Quan Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher

drm/amdgpu: Fix a typo in the include header guard of 'navi12_ip_offset.h'

2019-08-22T03:16:55+00:00

'_navi10_ip_offset_HEADER' is already used in 'navi10_ip_offset.h', so use '_navi12_ip_offset_HEADER' instead here. Reviewed-by: Xiaojie Yuan Signed-off-by: Christophe JAILLET Signed-off-by: Alex Deucher