<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/gpu/drm/amd/include/vi_structs.h, branch v6.6.132</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.132</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v6.6.132'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2021-03-24T02:59:25+00:00</updated>
<entry>
<title>drm/amdkfd: Check HIQ's MQD for queue preemption status</title>
<updated>2021-03-24T02:59:25+00:00</updated>
<author>
<name>Oak Zeng</name>
<email>Oak.Zeng@amd.com</email>
</author>
<published>2020-07-07T23:29:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=51a0f459f15fca1e1443de8d92431846872ee5cb'/>
<id>urn:sha1:51a0f459f15fca1e1443de8d92431846872ee5cb</id>
<content type='text'>
MEC firmware can silently fail the queue preemption request
without time out. In this case, HIQ's MQD's queue_doorbell_id
will be set. Check this field to see whether last queue preemption
was successful or not.

Signed-off-by: Oak Zeng &lt;Oak.Zeng@amd.com&gt;
Suggested-by: Jay Cornwall &lt;Jay.Cornwall@amd.com&gt;
Acked-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdkfd: Shift sdma_engine_id and sdma_queue_id in mqd</title>
<updated>2019-05-24T17:21:01+00:00</updated>
<author>
<name>Oak Zeng</name>
<email>ozeng@amd.com</email>
</author>
<published>2018-12-04T22:08:33+00:00</published>
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<id>urn:sha1:c6fd980ab154455df62adc89d81898d24654ab72</id>
<content type='text'>
FW of some new ASICs requires sdma mqd size to be not more than
128 dwords. Repurpose the last 2 reserved fields of sdma mqd for
driver internal use, so the total mqd size is no bigger than 128
dwords

Signed-off-by: Oak Zeng &lt;ozeng@amd.com&gt;
Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Implement amdgpu SDMA functions for VI</title>
<updated>2017-11-01T23:22:00+00:00</updated>
<author>
<name>Philip Cox</name>
<email>Philip.Cox@amd.com</email>
</author>
<published>2017-11-01T23:22:00+00:00</published>
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<id>urn:sha1:9807c3668500b0964e8ee59d68083675971bc224</id>
<content type='text'>
Signed-off-by: Philip Cox &lt;Philip.Cox@amd.com&gt;
Signed-off-by: shaoyun liu &lt;shaoyun.liu@amd.com&gt;
Signed-off-by: Yong Zhao &lt;yong.zhao@amd.com&gt;
Signed-off-by: Jay Cornwall &lt;Jay.Cornwall@amd.com&gt;
Signed-off-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Acked-by: Oded Gabbay &lt;oded.gabbay@gmail.com&gt;
Signed-off-by: Oded Gabbay &lt;oded.gabbay@gmail.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/gfx8: drop cz mqd</title>
<updated>2017-08-29T19:27:58+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-08-24T20:47:15+00:00</published>
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<id>urn:sha1:31bf29ab398be98891cc139ca6170575b973fa0d</id>
<content type='text'>
It was unused and according to hw team, it's the same for
all asics in a gfx family so remove it.

Reviewed-by: Felix Kuehling &lt;Felix.Kuehling@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/gfx8: fix spelling typo in mqd allocation</title>
<updated>2017-08-29T19:27:39+00:00</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2017-08-19T03:39:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2d6fb10565ca13e7a0f6f4725f1c3da5a99a2bcc'/>
<id>urn:sha1:2d6fb10565ca13e7a0f6f4725f1c3da5a99a2bcc</id>
<content type='text'>
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fix vulkan test performance drop and hang on VI</title>
<updated>2017-06-29T16:43:43+00:00</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-06-26T06:39:36+00:00</published>
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<id>urn:sha1:6b0fa871a9a2d83dd869ca40a7fd65a935d3564c</id>
<content type='text'>
caused by not program dynamic_cu_mask_addr in the KIQ MQD.

v2: create struct vi_mqd_allocation in FB which will contain
1. PM4 MQD structure.
2. Write Pointer Poll Memory.
3. Read Pointer Report Memory
4. Dynamic CU Mask.
5. Dynamic RB Mask.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/gfx8: move CE&amp;DE meta data structure to vi_structs.h</title>
<updated>2017-03-30T03:53:31+00:00</updated>
<author>
<name>Xiangliang Yu</name>
<email>Xiangliang.Yu@amd.com</email>
</author>
<published>2017-03-06T07:27:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=49abb980c5fafc75f10c2beb13c63a8b0f8bc44a'/>
<id>urn:sha1:49abb980c5fafc75f10c2beb13c63a8b0f8bc44a</id>
<content type='text'>
Because different HWs have different definition for CE &amp; DE meta
data, follow mqd design to move the structures to vi_structs.h.

And change the prefix from amdgpu to vi as the structures is only
for VI family.

Signed-off-by: Xiangliang Yu &lt;Xiangliang.Yu@amd.com&gt;
Reviewed-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: Add amdgpu &lt;--&gt; amdkfd gfx8 interface</title>
<updated>2015-07-20T06:16:48+00:00</updated>
<author>
<name>Ben Goz</name>
<email>ben.goz@amd.com</email>
</author>
<published>2014-10-07T11:43:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ff758a12b45b0513dbe9905deba2a29b20412138'/>
<id>urn:sha1:ff758a12b45b0513dbe9905deba2a29b20412138</id>
<content type='text'>
This patch adds the gfx8 interface file between amdgpu and amdkfd. This
interface file is currently in use when running on a Carrizo-based
system.

The interface itself is represented by a pointer to struct
kfd_dev. The pointer is located inside amdgpu_device structure.

All the register accesses that amdkfd need are done using this
interface. This allows us to avoid direct register accesses in
amdkfd proper, while also allows us to avoid locking between
amdkfd and amdgpu.

The single exception is the doorbells that are used in both of
the drivers. However, because they are located in separate pci
bar pages, the danger of sharing registers between the drivers
is minimal.

Having said that, we are planning to move the doorbells as well
to amdgpu.

Signed-off-by: Ben Goz &lt;ben.goz@amd.com&gt;
Signed-off-by: Oded Gabbay &lt;oded.gabbay@gmail.com&gt;
</content>
</entry>
</feed>
