kernel/linux.git/drivers/gpu/drm/amd/include/v9_structs.h, branch v6.12.80Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.802023-06-09T13:42:36+00:00drm/amdkfd: Update MQD management on multi XCC setup2023-06-09T13:42:36+00:00Mukul Joshimukul.joshi@amd.com2022-05-10T01:45:50+00:00urn:sha1:2f77b9a242a2e01822efc80c8b63eaa31df0f8b4
Update MQD management for both HIQ and user-mode compute
queues on a multi XCC setup. MQDs needs to be allocated,
initialized, loaded and destroyed for each XCC in the KFD
node.
v2: squash in fix "drm/amdkfd: Fix SDMA+HIQ HQD allocation on GFX9.4.3"
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Tested-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdkfd: Extend CU mask to 8 SEs (v3)2019-08-02T15:19:11+00:00Jay CornwallJay.Cornwall@amd.com2019-07-18T21:57:22+00:00urn:sha1:5145d57ec5f5cf7dadaa6ccd9c9f1e4dae82570b
Following bitmap layout logic introduced by:
"drm/amdgpu: support get_cu_info for Arcturus".
v2: squash in fixup for gfx_v9_0.c (Alex)
v3: squash in debug print output fix
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdkfd: Shift sdma_engine_id and sdma_queue_id in mqd2019-05-24T17:21:01+00:00Oak Zengozeng@amd.com2018-12-04T22:08:33+00:00urn:sha1:c6fd980ab154455df62adc89d81898d24654ab72
FW of some new ASICs requires sdma mqd size to be not more than
128 dwords. Repurpose the last 2 reserved fields of sdma mqd for
driver internal use, so the total mqd size is no bigger than 128
dwords
Signed-off-by: Oak Zeng <ozeng@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Update GFXv9 SDMA MQD structure2018-04-10T21:32:59+00:00Felix KuehlingFelix.Kuehling@amd.com2018-04-10T21:32:59+00:00urn:sha1:cf05fb8b144dae55d094b0fa7991e985a9b4561e
This matches what the HWS firmware expects on GFXv9 chips.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
drm/amdgpu/gfx9: adjust mqd allocation size2017-08-29T19:28:00+00:00Alex Deucheralexander.deucher@amd.com2017-08-19T03:52:37+00:00urn:sha1:ffe6d881e99413f3ebdfebf99570c2e840879e68
To allocate additional space for the dynamic cu masks.
Confirmed with the hw team that we only need 1 dword
for the mask. The mask is the same for each SE so
you only need 1 dword.
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/gfx9: update mqd to include dynamic CU mask2017-08-29T19:27:59+00:00Alex Deucheralexander.deucher@amd.com2017-08-19T03:36:08+00:00urn:sha1:29696bd680f196f52c6d5eedc4da4ef0482d8bb9
Necessary for proper operation with KIQ.
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/gfx9: impl gfx9 meta data emit2017-03-30T03:55:01+00:00Xiangliang YuXiangliang.Yu@amd.com2017-03-07T05:56:03+00:00urn:sha1:cca02cd3d40d11468f53c502c0579963b42d4f34
Insert ce meta prior to cntx_cntl and de follow it.
Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add MQD structs for GFX V92017-03-30T03:54:29+00:00Felix KuehlingFelix.Kuehling@amd.com2017-03-02T21:57:08+00:00urn:sha1:4b219123e9edd8b99809e0c7c0eb201f6e6fc655
This header defines the gfx v9 MEC structures.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>