Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.80 2024-09-10T21:27:17+00:00 2024-09-10T21:27:17+00:00 Alex Deucher alexander.deucher@amd.com 2024-09-06T14:42:45+00:00 urn:sha1:17ea4383649fdeaff3181ddcf1ff03350d42e591 Per the comments, these are variable sized arrays. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3613 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 81f7804ba84ee617ed594de934ed87bcc4f83531) Cc: stable@vger.kernel.org 2024-07-02T22:34:05+00:00 Alex Deucher alexander.deucher@amd.com 2024-07-01T16:50:10+00:00 urn:sha1:d0417264437a8fa05f894cabba5a26715b32d78e This is a variable sized array. Link: https://lists.freedesktop.org/archives/amd-gfx/2024-June/110420.html Tested-by: Jeff Layton <jlayton@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org 2024-05-29T21:02:41+00:00 Alex Deucher alexander.deucher@amd.com 2024-05-16T13:51:26+00:00 urn:sha1:05d9e24ddb15160164ba6e917a88c00907dc2434 Convert a variable sized array from [1] to []. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-05-22T16:01:39+00:00 Li Ma li.ma@amd.com 2024-05-20T10:43:55+00:00 urn:sha1:e64e8f7c178e5228e0b2dbb504b9dc75953a319f [Why] The vram width value is 0. Because the integratedsysteminfo table in VBIOS has updated to 2.3. [How] Driver needs a new intergrated info v2.3 table too. Then the vram width value will be correct. Signed-off-by: Li Ma <li.ma@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org 2024-02-22T15:26:32+00:00 Aurabindo Pillai aurabindo.pillai@amd.com 2024-01-29T22:20:53+00:00 urn:sha1:47136be6381c1c28b9e33b14849c9d1c7ec5e92e Add new firmware header definitions reqiured for DCN401 Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2023-08-31T22:09:38+00:00 Hawking Zhang Hawking.Zhang@amd.com 2023-08-23T09:41:44+00:00 urn:sha1:48d02dcba17aae6a1de4f9814aa5cbe4c977abbb To be used by aqua_vanjaram Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Candice Li <candice.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2023-06-09T13:44:25+00:00 Hawking Zhang Hawking.Zhang@amd.com 2022-05-27T05:47:24+00:00 urn:sha1:cd8d77f328c53aad8915c9c4d64cf557742bb257 hbm3 will be supported in some dgpu program Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Le Ma <Le.Ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-11-10T20:29:40+00:00 Tong Liu01 Tong.Liu01@amd.com 2022-11-10T09:31:36+00:00 urn:sha1:4864f2ee9ee2acf4a1009b58fbc62f17fa086d4e Move TMR region from top of FB to 2MB for FFBM, so we need to reserve TMR region firstly to make sure TMR can be allocated at 2MB Signed-off-by: Tong Liu01 <Tong.Liu01@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-06-03T20:43:36+00:00 Aurabindo Pillai aurabindo.pillai@amd.com 2022-02-21T20:34:41+00:00 urn:sha1:b801d8ad1b516a951535241c9cf60cac8f9a5c2b Add new structures for DCN 3.2.x. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2022-05-04T13:57:33+00:00 Hawking Zhang Hawking.Zhang@amd.com 2022-01-23T11:08:25+00:00 urn:sha1:21c8685b06d8cfb5709fb2cc0cae3a8f9331caea To match with smu v13_0_0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>