kernel/linux.git/drivers/gpu/drm/amd/include/asic_reg, branch v6.6.131

drm/amdgpu: Add additional DCE6 SCL registers

2025-10-19T14:30:44+00:00

[ Upstream commit 507296328b36ffd00ec1f4fde5b8acafb7222ec7 ] Fixes: 102b2f587ac8 ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)") Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amdgpu: Set snoop bit for SDMA for MI series

2025-06-04T12:42:10+00:00

[ Upstream commit 3394b1f76d3f8adf695ceed350a5dae49003eb37 ] SDMA writes has to probe invalidate RW lines. Set snoop bit in mmhub for this to happen. v2: Missed a few mmhub_v9_4. Added now. v3: Calculate hub offset once since it doesn't change inside the loop Modified function names based on review comments. Signed-off-by: Harish Kasiviswanathan Reviewed-by: Philip Yang Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin

drm/amdgpu: Force order between a read and write to the same address

2023-12-08T07:52:17+00:00

commit 4b27a33c3b173bef1d19ba89e0b9b812b4fddd25 upstream. Setting register to force ordering to prevent read/write or write/read hazards for un-cached modes. Signed-off-by: Alex Sierra Acked-by: Alex Deucher Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.1.x Signed-off-by: Greg Kroah-Hartman

drm/amd/display: Add some missing register definitions

2023-08-15T22:08:28+00:00

[Why&How] Add some missing register definitions and rearrange some others to maintain consistency with related definitions. Acked-by: Stylon Wang Signed-off-by: Aurabindo Pillai Reviewed-by: Rodrigo Siqueira Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amdgpu: Add pci usage to nbio v7.9

2023-08-09T13:46:05+00:00

Add implementation to get pcie usage for nbio v7.9. Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Shiwu Zhang Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: add ih 6.1 registers

2023-08-07T20:35:31+00:00

Add new registers. v2: updates (Alex) Signed-off-by: Ben Li Signed-off-by: Alex Deucher

drm/amdgpu: setup hw debug registers on driver initialization

2023-06-09T16:34:56+00:00

Add missing debug trap registers references and initialize all debug registers on boot by clearing the hardware exception overrides and the wave allocation ID index. The debugger requires that TTMPs 6 & 7 save the dispatch ID to map waves onto dispatch during compute context inspection. In order to correctly set this up, set the special reserved CP bit by default whenever the MQD is initailized. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: Disable interrupt tracker on NBIOv7.9

2023-06-09T14:45:23+00:00

Enabling nBIF interrupt history tracker prevents LCLK deep sleep, hence disable it Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: Add gc v9_4_3 ras error status registers

2023-06-09T14:37:34+00:00

GC v9_4_3 introduces UE|CE_ERR_STATUS_LO|HI to log hardware errors Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher

drm/amdgpu: Add vcn/jpeg ras err status registers

2023-06-09T13:58:12+00:00

Add new ras error status registers introduced in vcn v4_0_3 to log vcn and jpeg ras error. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou Signed-off-by: Alex Deucher