kernel/linux.git/drivers/gpu/drm/amd/include/asic_reg, branch v6.12.80Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.12.802025-10-19T14:33:42+00:00drm/amdgpu: Add additional DCE6 SCL registers2025-10-19T14:33:42+00:00Alex Deucheralexander.deucher@amd.com2025-09-25T18:45:21+00:00urn:sha1:9626d3af3cd1fe79401ceb82039ed10450867a55
[ Upstream commit 507296328b36ffd00ec1f4fde5b8acafb7222ec7 ]
Fixes: 102b2f587ac8 ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drm/amdgpu: Set snoop bit for SDMA for MI series2025-05-29T09:02:52+00:00Harish KasiviswanathanHarish.Kasiviswanathan@amd.com2025-02-04T22:57:47+00:00urn:sha1:452807a863018375186790bed955382b6bd5829e
[ Upstream commit 3394b1f76d3f8adf695ceed350a5dae49003eb37 ]
SDMA writes has to probe invalidate RW lines. Set snoop bit in mmhub for
this to happen.
v2: Missed a few mmhub_v9_4. Added now.
v3: Calculate hub offset once since it doesn't change inside the loop
Modified function names based on review comments.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drm/amd: Add some missing straps from NBIO 7.11.02024-12-09T09:41:14+00:00Mario Limonciellomario.limonciello@amd.com2024-11-18T17:46:10+00:00urn:sha1:be51376b1f500f455d7403590b5e617f2f1444cd
commit 902fbbf429b8213232b18de0ddfd5c0f3851cb8f upstream.
Earlier ASICs have strap information exported, and this is missing
for NBIO 7.11.0.
Cc: stable@vger.kernel.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Fixes: ca8c68142ad8 ("drm/amdgpu: add nbio 7.11 registers")
Link: https://lore.kernel.org/r/20241118174611.10700-1-mario.limonciello@amd.com
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drm/amdgpu/uvd4: fix mask and shift definitions2024-08-13T14:26:48+00:00Remington Brasgarbrasga@uci.edu2024-07-31T05:54:51+00:00urn:sha1:3834ce360067b4ee98fdef14571923500a0499a4
A few define's are listed twice with different, incorrect values.
This fix sets them appropriately.
Signed-off-by: Remington Brasga <rbrasga@uci.edu>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Fix atomics on GFX122024-07-23T21:33:17+00:00David Belangerdavid.belanger@amd.com2024-06-10T20:38:55+00:00urn:sha1:666f14cab21b17ccc1bdfe1e82458aa429b3b7e0
If PCIe supports atomics, configure register to prevent DF from
breaking atomics in separate load/store operations.
Signed-off-by: David Belanger <david.belanger@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add some missing register definitions2024-06-27T21:32:17+00:00Aurabindo Pillaiaurabindo.pillai@amd.com2024-06-25T18:17:46+00:00urn:sha1:ad89e904e3aaa93628785546034ec77f3100cf79
Add some register offsets that are required for Display DCC on DCN401
Fixes: 2d072b445622 ("drm/amd: Add reg definitions for DCN401 DCC")
Reported-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add reg definitions for DCN401 DCC2024-06-27T21:10:38+00:00Aurabindo Pillaiaurabindo.pillai@amd.com2024-06-14T19:42:55+00:00urn:sha1:2d072b445622b90f8a961c0376887120da75221f
[WHAT]
Add the necessary register definitions to enable DCC on DCN4x
Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: update gc_12_0_0 headers2024-06-05T15:03:10+00:00Alex Deucheralexander.deucher@amd.com2024-05-31T15:57:00+00:00urn:sha1:b592d01df6efa2a4a93e360358b1f45057c80dda
Add some additional registers.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add missing registers for DCN4012024-05-29T18:40:39+00:00Rodrigo SiqueiraRodrigo.Siqueira@amd.com2024-05-17T19:10:20+00:00urn:sha1:d0a6d85072b02c02697bc60f2115756aa1bf89d8
Add some additional registers.
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add missing offsets in gc_11_0_0_offset.h2024-05-23T19:13:34+00:00Sunil Khatrisunil.khatri@amd.com2024-05-21T13:43:44+00:00urn:sha1:eb14b8f50516b543b3483a14b1f30001940e6305
IB1 registers:
regCP_IB1_CMD_BUFSZ
regCP_IB1_BASE_LO
regCP_IB1_BASE_HI
regCP_IB1_BUFSZ
regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR
Above registers are part of the asic but not of
the offset file for gc_11_0_0_offset.h and hence
adding them.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>