kernel/linux.git/drivers/gpu/drm/amd/include/asic_reg, branch v6.1.60Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.1.602022-10-11T15:05:35+00:00drm/amdgpu: Update umc v8_10_0 headers2022-10-11T15:05:35+00:00Candice Licandice.li@amd.com2022-09-26T08:18:56+00:00urn:sha1:6dddc1eb9632b0eb6098d1dc849e8acb2408c1b6
Add GeccCtrl offset and mask to umc v8_10_0 headers.
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add missing XGMI hive registers for mmhub 9.4.12022-09-29T13:41:43+00:00Tom St Denistom.stdenis@amd.com2022-09-23T12:55:50+00:00urn:sha1:82806c25d5e9d927ecb68c0c3679dd41187c9af6
These are used by umr to sort the hive nodes since the kernel
initializes the nodes in order of bus enumeration not XGMI hive
enumeration.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: update GC 10.3.0 pwrdec2022-09-13T16:54:23+00:00Tom St Denistom.stdenis@amd.com2022-09-08T13:36:18+00:00urn:sha1:1ed1f6be6eb3daa8097d6419dde516c9854a8790
The 10.3 GC headers were missing most of the pwrdec block.
This patch adds the registers and bits present in the 10.1 header
but based on the contents of the 10.3 specs.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add missing CGTS*TCC_DISABLE to 10.3 headers2022-09-08T02:28:42+00:00Tom St Denistom.stdenis@amd.com2022-09-07T14:18:01+00:00urn:sha1:780244a2fe8a82424c85f4cb15e45d0bbeec8f26
The TCC_DISABLE registers were not included in the 10.3 headers and
instead just placed directly in the gfx_v10_0.c source. This patch
adds them to the headers so tools like umr can scan them and support them.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add gc v11_0_3 ip headers2022-08-30T20:36:42+00:00Frank MinFrank.Min@amd.com2022-06-27T03:05:43+00:00urn:sha1:a40a92af46113e200b9110c4040a465771d28b35
Add gc v11_0_3 register offset and shift masks
header files
v2: update registers (Alex)
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.02022-08-22T20:47:09+00:00Tim Huangtim.huang@amd.com2022-08-15T05:03:49+00:00urn:sha1:6575eb930d16b789a0230df5664578d7d159a255
Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro
definitions for AMD_CG_SUPPORT_BIF_LS.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: save and restore gc hub regs2022-08-16T22:14:31+00:00Victor ZhaoVictor.Zhao@amd.com2022-06-21T08:59:44+00:00urn:sha1:bfaced6ee77484d8b9c6baf86a8e9406f80108c5
Save and restore gfxhub regs as they will be reset during mode 2
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add header files for MP 13.0.42022-07-29T19:24:38+00:00Xiaojian DuXiaojian.Du@amd.com2022-07-28T05:23:38+00:00urn:sha1:492af34c9f67ef864319d0db930c8518a04b1937
This patch will add header files for MP 13.0.4.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: add additional page fault settings for gfx112022-07-28T20:19:59+00:00Chengming GuiJack.Gui@amd.com2022-06-20T07:52:29+00:00urn:sha1:7c8e4a257246399c4f1ff43a06fc53ec53423754
Add three additional page fault settings.
V2: move reg offset definition to header file. (Alex)
V3: add all shift/mask definitions of used reg. (Hawking)
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add umc v8_10_0 ip headers2022-07-18T20:37:38+00:00YiPeng ChaiYiPeng.Chai@amd.com2022-07-04T09:16:38+00:00urn:sha1:75510fac07cdde23c9217c8299b6cd64c689fb2b
Add umc v8_10_0 register offset and shift masks
header files
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>