kernel/linux.git/drivers/gpu/drm/amd/include/asic_reg, branch v5.6.11Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v5.6.112020-02-25T16:30:42+00:00amdgpu/gmc_v9: save/restore sdpif regs during S32020-02-25T16:30:42+00:00Shirish Sshirish.s@amd.com2020-01-27T11:05:24+00:00urn:sha1:a3ed353cf8015ba84a0407a5dc3ffee038166ab0
fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM.
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for Arcturus2020-01-30T22:15:27+00:00Joseph GreathouseJoseph.Greathouse@amd.com2020-01-27T22:08:11+00:00urn:sha1:18c6b74e7cfc9a599917d9e98f9835de8208e19a
In previous gfx9 parts, S_BARRIER shader instructions are implicitly
S_WAITCNT 0 instructions as well. This setting turns off that
mechanism in Arcturus and beyond. With this, shaders must follow the
ISA guide insofar as putting in explicit S_WAITCNT operations even
after an S_BARRIER.
v2: Fix patch title to list component
Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add EDC counter registers of gc for Arcturus2020-01-22T21:36:22+00:00Dennis LiDennis.Li@amd.com2020-01-16T04:30:33+00:00urn:sha1:19cf0dd4b9d2771015fc9d74ec1b0b9203cf8c5a
add reg headers to gc includes
v2: remove unused registers and fields in this patch set
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: update mmhub 9.4.1 header files for Acrturus2020-01-22T21:35:42+00:00Dennis LiDennis.Li@amd.com2020-01-13T08:15:38+00:00urn:sha1:f519cd13c23e8c884011295b205c1463babbf416
Add mask & shift definition of MAM_D(0~3)MEM for all mmhub
ranges.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: added support to get mGPU DRAM base2020-01-22T21:34:07+00:00John Clementsjohn.clements@amd.com2020-01-17T04:18:00+00:00urn:sha1:a6c44d2538c469f412c3fded0de2290494d762d7
resolves issue with RAS error injection in mGPU configuration
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include: Add OCSC registers2020-01-16T18:41:06+00:00Rodrigo SiqueiraRodrigo.Siqueira@amd.com2020-01-07T20:28:43+00:00urn:sha1:d1dcb05f0e45f97061d5c1f921aa038f1ae92c7b
Add registers for handling Post Gamma Color Blending (OCSC), which is
useful for conversion from RGB->YUV for HDMI.
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add defines for DF and TCP Hashing2020-01-14T15:18:41+00:00Joseph GreathouseJoseph.Greathouse@amd.com2020-01-09T23:07:12+00:00urn:sha1:ae99fc35ceea9ae9c496987d113187464b33b2b8
On Arcturus, we need TC channel hashing, which is set by the
driver, to match DF hashing, which is set by VBIOS. To match
these, we plan to query the DF information and then properly
set the TC configuration bits to match them.
This patch adds the required fields to register definitions
in preparation for a future patch which will use them.
Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: add missing umc_6_1_2_sh_mask.h header file (v2)2020-01-14T15:18:09+00:00Tom St Denistom.stdenis@amd.com2020-01-09T15:37:56+00:00urn:sha1:351d5ac55c72ee6f6ad018e2a756b5fe09fceed3
(v2): Fix preprocessor tag
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add MCUMC_ADDRT0 offset to ip header file2020-01-14T15:18:09+00:00Guchun Chenguchun.chen@amd.com2020-01-08T05:50:10+00:00urn:sha1:817396dc9f6ab2481b94071de2e586aae876e89c
Both are needed on vega20 and arcturus chip.
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support Arcturus2019-12-23T19:56:37+00:00James ZhuJames.Zhu@amd.com2019-12-16T20:31:07+00:00urn:sha1:6eed6cc142345d0e7da4d54d0a58c28074ec29a3
Arcturus has 8 SEs. Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7
for EDC GPR _workarounds,
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Yong Zhao <Yong.Zhao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>