kernel/linux.git/drivers/gpu/drm/amd/include/asic_reg, branch v4.18.10Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v4.18.102018-06-13T18:45:23+00:00drm/amd/include: Update df 3.6 mask and shift definition2018-06-13T18:45:23+00:00Shaoyun LiuShaoyun.Liu@amd.com2018-06-12T17:35:44+00:00urn:sha1:b0f6b8090e05a24263207a399b6c48a94034f1e8
The register field hsas been changed in df 3.6, update to correct setting
Signed-off-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add new DF 1.7 register defs2018-05-24T04:51:20+00:00Alex Deucheralexander.deucher@amd.com2018-05-10T19:45:12+00:00urn:sha1:99631045862e2994b47285a8cc96bc939ae5b42f
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add df 3.6 headers2018-05-18T21:08:15+00:00Alex Deucheralexander.deucher@amd.com2018-05-14T16:50:46+00:00urn:sha1:9883e9d751dad05e8c3ad3c6b769dafc60762c38
Needed for vega20.
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Add dce-12.1 gpio aux registers (v2)2018-05-17T15:13:19+00:00Roman LiRoman.Li@amd.com2018-02-14T22:20:54+00:00urn:sha1:d82420b56a17d5b39579bc46f8dad757be684f94
Updating dce12 register headers by adding dc registers
required for potential DP LTTPR support.
v2: fix mode change
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add df v1_7 header files2018-04-11T18:07:53+00:00Hawking ZhangHawking.Zhang@amd.com2018-03-28T08:23:28+00:00urn:sha1:3ef1381d4e7ddd3e063cf6fd33df96badfb66839
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: Add CM_TEST_DEBUG regs for DCN2018-04-11T18:07:35+00:00Harry Wentlandharry.wentland@amd.com2018-03-15T20:40:02+00:00urn:sha1:86993018d7d23b934d1c884be0fbf0bcfa15b8c5
We'd like to use them for reading DCN debug status.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include: Add ip header files for vega12.2018-03-21T19:23:01+00:00Feifei XuFeifei.Xu@amd.com2017-10-16T10:09:14+00:00urn:sha1:133f97945f679ae0040a50f5933ef9a6563cb30b
Add ip header files for IPs with a delta for vg12:
GC, MMHUB, OSS
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-By: Ken Wang <ken.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: re-add missing GC 9.1 and SDMA0 4.1 sh_mask header files2018-03-07T21:10:13+00:00Tom St Denistom.stdenis@amd.com2018-03-06T15:52:41+00:00urn:sha1:8113cf9cab1713e8b711f195bf673206f44fa050
These are required by umr to properly parse bitfield offsets.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexdeucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Adding missing TMZ sh/mask entries for DCN1 SURFACE_CONTROL2018-02-19T19:19:21+00:00Harry Wentlandharry.wentland@amd.com2018-01-25T21:06:41+00:00urn:sha1:d89746ec4fcc16aac75bb51f43f9452d95bf7a31
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <tony.cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/pp: Export registers for read vddc on VI/Vega102018-02-19T19:17:49+00:00Rex ZhuRex.Zhu@amd.com2018-01-02T06:06:05+00:00urn:sha1:680731ade574e770e16f4488eb4217e8b8b13ffe
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>