kernel/linux.git/drivers/gpu/drm/amd/include/asic_reg/gc, branch v6.3.2Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v6.3.22023-01-17T21:11:50+00:00amd/amdgpu: Add RLC_RLCS_FED_STATUS_* to gc v11_0_3 ip headers2023-01-17T21:11:50+00:00YiPeng ChaiYiPeng.Chai@amd.com2023-01-05T06:52:51+00:00urn:sha1:79d949a2d688b09b1ff840a2366a8cfe1b7a2651
V2:
Add RLC_RLCS_FED_STATUS_0 and RLC_RLCS_FED_STATUS_1 register
offset and shift masks.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: update GC 10.3.0 pwrdec2022-09-13T16:54:23+00:00Tom St Denistom.stdenis@amd.com2022-09-08T13:36:18+00:00urn:sha1:1ed1f6be6eb3daa8097d6419dde516c9854a8790
The 10.3 GC headers were missing most of the pwrdec block.
This patch adds the registers and bits present in the 10.1 header
but based on the contents of the 10.3 specs.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add missing CGTS*TCC_DISABLE to 10.3 headers2022-09-08T02:28:42+00:00Tom St Denistom.stdenis@amd.com2022-09-07T14:18:01+00:00urn:sha1:780244a2fe8a82424c85f4cb15e45d0bbeec8f26
The TCC_DISABLE registers were not included in the 10.3 headers and
instead just placed directly in the gfx_v10_0.c source. This patch
adds them to the headers so tools like umr can scan them and support them.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add gc v11_0_3 ip headers2022-08-30T20:36:42+00:00Frank MinFrank.Min@amd.com2022-06-27T03:05:43+00:00urn:sha1:a40a92af46113e200b9110c4040a465771d28b35
Add gc v11_0_3 register offset and shift masks
header files
v2: update registers (Alex)
Signed-off-by: Frank Min <Frank.Min@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: save and restore gc hub regs2022-08-16T22:14:31+00:00Victor ZhaoVictor.Zhao@amd.com2022-06-21T08:59:44+00:00urn:sha1:bfaced6ee77484d8b9c6baf86a8e9406f80108c5
Save and restore gfxhub regs as they will be reset during mode 2
Signed-off-by: Victor Zhao <Victor.Zhao@amd.com>
Acked-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: add additional page fault settings for gfx112022-07-28T20:19:59+00:00Chengming GuiJack.Gui@amd.com2022-06-20T07:52:29+00:00urn:sha1:7c8e4a257246399c4f1ff43a06fc53ec53423754
Add three additional page fault settings.
V2: move reg offset definition to header file. (Alex)
V3: add all shift/mask definitions of used reg. (Hawking)
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add gc v11_0_0 ip headers v112022-04-28T21:48:28+00:00Hawking ZhangHawking.Zhang@amd.com2021-12-30T08:56:09+00:00urn:sha1:f33ac92f9c010be84ecbbec7e30990012be806e8
Add gc v11_0_0 register offset and shift masks
header files (Hawking)
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: add regCP_MEx_INT_STAT_DEBUG for Aldebaran debugging2021-08-06T01:17:59+00:00Tom St Denistom.stdenis@amd.com2021-03-23T16:22:45+00:00urn:sha1:d2a266fad506aa3dc143280dcf2dd732b40bcdd3
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: only harvest gcea/mmea error status in arcturus2021-04-21T01:35:45+00:00Hawking ZhangHawking.Zhang@amd.com2021-04-16T09:34:13+00:00urn:sha1:53ee6609b42e09f89bf2cdd15a340c236694ecd3
SDP RdRspStatus/WrRspStatus or first parity error on
RdRsp data can cause system fatal error in arcturus.
GPU will be freezed in such case.
Driver needs to harvest these error information before
reset the GPU. Check error type to avoid harvest normal
gcea/mmea information.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Stanley Yang <Stanley.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headers2021-04-09T20:46:59+00:00Tom St Denistom.stdenis@amd.com2021-03-26T11:07:25+00:00urn:sha1:53df89ddc0ccb016edbf8c4cc1d66e75ade28837
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>