kernel/linux.git/drivers/gpu/drm/amd/include/asic_reg/df, branch v6.18.22

drm/amdgpu: Fix atomics on GFX12

2024-07-24T21:30:23+00:00

If PCIe supports atomics, configure register to prevent DF from breaking atomics in separate load/store operations. Signed-off-by: David Belanger Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher (cherry picked from commit 666f14cab21b17ccc1bdfe1e82458aa429b3b7e0)

drm/amdgpu: Add df v4_3 headers

2022-12-15T17:19:22+00:00

Add df v4_3 header files. Signed-off-by: Candice Li Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: add poison mode query for DF (v2)

2021-09-28T13:30:06+00:00

Add ras poison mode query interface for DF. v2: replace RREG32_PCIE with RREG32_SOC15. Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher

drm/amdgpu: Query correct register for DF hashing on Aldebaran

2021-05-20T02:44:19+00:00

For Aldebaran, driver needs to query DramMegaBaseAddress to check if DF hashing is enabled. Signed-off-by: Mukul Joshi Acked-by: Alex Deucher Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alex Deucher

drm/amdgpu: Enable TCP channel hashing for Aldebaran

2021-05-10T22:07:20+00:00

Enable TCP channel hashing to match DF hash settings for Aldebaran. Signed-off-by: Mukul Joshi Signed-off-by: Oak Zeng Reviewed-by: Joseph Greathouse Reviewed-by: Harish Kasiviswanathan Signed-off-by: Alex Deucher

drm/amdgpu: added support to get mGPU DRAM base

2020-01-22T21:34:07+00:00

resolves issue with RAS error injection in mGPU configuration Reviewed-by: Hawking Zhang Signed-off-by: John Clements Signed-off-by: Alex Deucher

drm/amdgpu: add defines for DF and TCP Hashing

2020-01-14T15:18:41+00:00

On Arcturus, we need TC channel hashing, which is set by the driver, to match DF hashing, which is set by VBIOS. To match these, we plan to query the DF information and then properly set the TC configuration bits to match them. This patch adds the required fields to register definitions in preparation for a future patch which will use them. Signed-off-by: Joseph Greathouse Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu: add perfmons accessible during df c-states

2019-12-23T19:55:53+00:00

During DF C-State, Perfmon counters outside of range 1D700-1D7FF will encounter SLVERR affecting xGMI performance monitoring. PerfmonCtr[7:4] is being added to avoid SLVERR during read since it falls within this range. PerfmonCtl[7:4] is being added in order to arm PerfmonCtr[7:4]. Since PerfmonCtl[7:4] exists outside of range 1D700-1D7FF, DF routines will be enabled to opportunistically re-arm PerfmonCtl[7:4] on retry after SLVERR. Signed-off-by: Jonathan Kim Acked-by: Alex Deucher Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher

drm/amdgpu: exposing fica registers to df offsets

2019-07-18T19:18:07+00:00

exposing fica registers to poll df pie data for xgmi error counters for vega20. Signed-off-by: Jonathan Kim Reviewed-by: Alexander Deucher Signed-off-by: Alex Deucher

drm/amdgpu: add df perfmon regs and funcs for xgmi

2019-05-24T17:20:50+00:00

v6: Squash in warning fix (Colin Ian King) v5: Fix warnings (Alex) v4: fixed mixed delaration and code warnings and minor errors v3: exposing df funcs in amdgpu_df_funcs in amdgpu.h v2: moving permonctl/perfmonctr from default to offset - adding df perfmonctl and perfmonctr registers for df counters - adding df funcs to set perfmonctl and get perfmonctr for df and xgmi counters - exposing df funcs in amdgpu_df_funcs Signed-off-by: Jonathan Kim Reviewed-by: Evan Quan Signed-off-by: Alex Deucher