Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.0.y 2025-05-28T20:01:50+00:00 2025-05-28T20:01:50+00:00 Aurabindo Pillai aurabindo.pillai@amd.com 2025-05-21T19:59:56+00:00 urn:sha1:d78eb800f8f5169db89a28380631aefc224a76bb Add some HDCP related register headers for future use. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2025-02-13T02:04:07+00:00 Wayne Lin Wayne.Lin@amd.com 2025-01-10T12:10:34+00:00 urn:sha1:9b194af117a85a603321a3834636f1a8195a2c35 [Why & How] Add register headers for DCN36. V2: adjust copyright license text Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-12-10T15:37:34+00:00 Leo Li sunpeng.li@amd.com 2024-12-05T20:43:42+00:00 urn:sha1:ecc5278ce05d18fb0a2e167ead91394356cb4c79 They were named with the incorrect dcn version. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Sun peng Li <sunpeng.li@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-11-04T16:40:21+00:00 Aurabindo Pillai aurabindo.pillai@amd.com 2024-11-01T16:16:18+00:00 urn:sha1:c7b4ecc1fa29235e5a14ad178ab96ef15a0d16f6 Add a mising reg field to the autogenerated header for future use Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-06-27T21:32:17+00:00 Aurabindo Pillai aurabindo.pillai@amd.com 2024-06-25T18:17:46+00:00 urn:sha1:ad89e904e3aaa93628785546034ec77f3100cf79 Add some register offsets that are required for Display DCC on DCN401 Fixes: 2d072b445622 ("drm/amd: Add reg definitions for DCN401 DCC") Reported-by: Tom St Denis <tom.stdenis@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-06-27T21:10:38+00:00 Aurabindo Pillai aurabindo.pillai@amd.com 2024-06-14T19:42:55+00:00 urn:sha1:2d072b445622b90f8a961c0376887120da75221f [WHAT] Add the necessary register definitions to enable DCC on DCN4x Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-05-29T18:40:39+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2024-05-17T19:10:20+00:00 urn:sha1:d0a6d85072b02c02697bc60f2115756aa1bf89d8 Add some additional registers. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-04-26T21:23:08+00:00 Aurabindo Pillai aurabindo.pillai@amd.com 2024-03-26T18:41:52+00:00 urn:sha1:59a0c03a50e7f058e599c313e6a129562147016d Update register headers. Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-04-26T21:22:42+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2024-04-09T21:25:23+00:00 urn:sha1:5e66f6eaa290093c4542ed216c298000713f92e5 This commit add some missing HDMI control registers to DCN3x. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2024-04-10T02:06:16+00:00 Rodrigo Siqueira Rodrigo.Siqueira@amd.com 2024-03-22T19:56:26+00:00 urn:sha1:be239684b18e1cdcafcf8c7face4a2f562c745ad Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>